公开(公告)号：US6061767A

公开(公告)日：2000-05-09

申请号：US993531

申请日：1997-12-18

Applicant: Jerry Chun-Jen Kuo ,  Po-Shen Lai ,  Autumn Jane Niu

Inventor： Jerry Chun-Jen Kuo ,  Po-Shen Lai ,  Autumn Jane Niu

IPC: H04L12/56 ,  G06F12/00

CPC classification number: H04L49/9047 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9021

Abstract: A network interface device having a random access memory for buffering data between a host bus interface and a media access controller includes a buffer controller configured for storing a data frame in combination with tracking and status information associated with the storage of the data frame. The memory controller is configured for writing receive frame data received from a media access controller into the random access memory. The tracking and status information is stored in memory locations contiguous with the data frame to enable a read controller operating in a separate clock domain to access the status information and the corresponding data frame as a single data unit. Moreover, the disclosed embodiment stores the status information at the beginning of the stored data unit, enabling a controller reading the buffer memory to immediately determine the status of the corresponding stored data frame.

Abstract translation: 具有用于在主机总线接口和媒体访问控制器之间缓存数据的随机存取存储器的网络接口设备包括：缓冲器控制器，被配置为与跟踪数据帧和与数据帧的存储相关联的状态信息结合存储数据帧。 存储器控制器被配置为将从媒体访问控制器接收的接收帧数据写入随机存取存储器。 跟踪和状态信息存储在与数据帧相邻的存储器位置中，以使得在单独的时钟域中操作的读取控制器可以将状态信息和相应的数据帧作为单个数据单元访问。 此外，所公开的实施例将状态信息存储在所存储的数据单元的开始处，使得读取缓冲存储器的控制器能够立即确定对应的存储数据帧的状态。

公开(公告)号：US06279044B1

公开(公告)日：2001-08-21

申请号：US09150678

申请日：1998-09-10

Applicant: Autumn Jane Niu ,  Jerry Chun-Jen Kuo

Inventor： Autumn Jane Niu ,  Jerry Chun-Jen Kuo

IPC: G06F300

CPC classification number: G06F5/00

Abstract: A network interface for a workstation is configured to supply data to a host bus. The network interface includes a buffer memory for storing a data frame received from a network according to a first byte alignment. A bus interface unit is configured to output the data frame onto the host bus according to a second byte alignment based on a master or slave transfer request to access the buffer memory. The slave request to access the buffer memory may be in the form of either an I/O mapped or memory mapped request. A memory management unit includes request logic to receive the master and slave transfer requests and generate a generic request to access the buffer memory. The memory management unit is configured to transfer the data frame from the buffer memory in response to the generic request. The bus interface unit includes a byte packing circuit configured for changing a byte alignment of the data frame prior to its transfer to the host memory. The byte alignment is changed based on information associated with the generic request. Hence, the amount of logic necessary to service the various types of requests is minimized.

Abstract translation: 工作站的网络接口被配置为向主机总线提供数据。 网络接口包括缓冲存储器，用于根据第一字节对准存储从网络接收的数据帧。 总线接口单元被配置为基于访问缓冲存储器的主或从传输请求，根据第二字节对准将数据帧输出到主机总线上。 访问缓冲存储器的从站请求可以是I / O映射或存储器映射请求的形式。 存储器管理单元包括用于接收主从传输请求的请求逻辑，并产生访问缓冲存储器的通用请求。 存储器管理单元被配置为响应于通用请求从缓冲存储器传送数据帧。 总线接口单元包括字节打包电路，该字节打包电路被配置为在将数据帧传送到主机存储器之前改变数据帧的字节对齐。 基于与通用请求相关联的信息来改变字节对齐。 因此，使各种类型的请求所需的逻辑量最小化。

公开(公告)号：US6061768A

公开(公告)日：2000-05-09

申请号：US993891

申请日：1997-12-18

Applicant: Jerry Chun-Jen Kuo ,  Autumn Jane Niu ,  Po-Shen Lai

Inventor： Jerry Chun-Jen Kuo ,  Autumn Jane Niu ,  Po-Shen Lai

IPC: G06F13/38 ,  G06F13/00

CPC classification number: G06F13/387

Abstract: A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memory between the read and write controllers. The synchronization circuit determines the presence of a stored frame in the random access memory by asynchronously comparing write counter and read counter values stored in gray code counters, where each counter is configured for changing a single bit of a counter value in response to an increment signal. The determined presence of one or more stored data frames is used to arbitrate storage of tracking information by either the read controller or the write controller into a holding register used to determine a read status for the random access memory.

Abstract translation: 网络接口设备包括用作发送和接收缓冲器的随机存取存储器，用于在主计算机总线和分组交换网络之间传输和接收数据帧。 网络接口设备包括用于每个发送和接收缓冲器的读和写控制器，其中每个写控制器在与相应的读控制器分离的时钟域中操作。 存储器管理单元还包括同步电路，其控制仲裁以访问读取和写入控制器之间的随机存取存储器。 同步电路通过异步比较存储在灰度代码计数器中的写入计数器和读取计数器值来确定随机存取存储器中存储的帧的存在，其中每个计数器被配置为响应于增量信号来改变计数器值的单个位 。 所确定的一个或多个存储的数据帧的存在被用于将读取控制器或写入控制器的跟踪信息的存储仲裁为用于确定随机存取存储器的读取状态的保持寄存器。