公开(公告)号：US06542512B1

公开(公告)日：2003-04-01

申请号：US09346745

申请日：1999-07-02

Applicant: Jenny Liu Fischer ,  Ching Yu ,  Jerry Chun-Jen Kuo ,  Po-Shen Lai ,  Autumn Jane Niu ,  Ian Lam

Inventor： Jenny Liu Fischer ,  Ching Yu ,  Jerry Chun-Jen Kuo ,  Po-Shen Lai ,  Autumn Jane Niu ,  Ian Lam

IPC: H04L1228

CPC classification number: H04L49/901 ,  H04L47/50 ,  H04L49/3027 ,  H04L49/351 ,  H04L49/90

Abstract: A network switch in a packet switched network includes a plurality of network switch ports, each configured for sending and receiving data packets between a medium interface and the network switch. The network switch port includes an IEEE 802.3 compliant transmit state machine and receive state machine configured for transmitting and receiving network data to and from a medium interface, such as a reduced medium independent interface, respectively. The network switch port also includes a memory management unit configured for selectively transferring the network data between the transmit and receive state machines and a random access transmit buffer and a random access receive buffer, respectively. The transmit state machine outputs a flush transmit buffer signal to the transmit memory management unit in response to a detected error in transmitting the transmit data. The transmit memory management unit, in response to the flush transmit buffer signal, sets an incremented transmit buffer pointer value to a buffer pointer value corresponding to a next transmit data stored in the transmit buffer.

Abstract translation: 分组交换网络中的网络交换机包括多个网络交换机端口，每个网络交换机端口被配置为在介质接口和网络交换机之间发送和接收数据分组。 网络交换机端口包括符合IEEE 802.3标准的传输状态机和接收状态机，其配置用于分别向介质接口（例如简化介质独立接口）发送和接收网络数据。 网络交换机端口还包括配置用于分别在发送和接收状态机与随机接入发送缓冲器和随机接入接收缓冲器之间选择性地传送网络数据的存储器管理单元。 发送状态机响应于发送发送数据中检测到的错误，向发送存储器管理单元输出清空发送缓冲器信号。 发送存储器管理单元响应于刷新发送缓冲器信号，将增加的发送缓冲器指针值设置为对应于存储在发送缓冲器中的下一个发送数据的缓冲器指针值。

公开(公告)号：US06463542B1

公开(公告)日：2002-10-08

申请号：US09321834

申请日：1999-05-28

Applicant: Ching Yu ,  Jerry Chun-Jen Kuo ,  Jeffrey Dwork ,  Din-I Tsai

Inventor： Ching Yu ,  Jerry Chun-Jen Kuo ,  Jeffrey Dwork ,  Din-I Tsai

IPC: G06F100

CPC classification number: G06F1/3209

Abstract: A novel method of power management is provided in a computer system having a network interface module including a buffer memory and a MAC block. The method includes determining whether the system is inactive during a predetermined time period. If so, activity of the MAC block is checked. If the MAC block is idle, the status of the buffer memory is determined. The system is placed into a power-down mode if the buffer memory is empty.

Abstract translation: 在具有包括缓冲存储器和MAC块的网络接口模块的计算机系统中提供了一种新颖的电源管理方法。 该方法包括在预定时间段内确定系统是否不活动。 如果是，则检查MAC块的活动。 如果MAC块空闲，则确定缓冲存储器的状态。 如果缓冲存储器为空，则将系统置于掉电模式。

公开(公告)号：US6128308A

公开(公告)日：2000-10-03

申请号：US993063

申请日：1997-12-18

Applicant: Jerry Chun-Jen Kuo ,  Autumn Jane Niu ,  Po-Shen Lai

Inventor： Jerry Chun-Jen Kuo ,  Autumn Jane Niu ,  Po-Shen Lai

IPC: H04L12/413 ,  H04L12/56 ,  H04L12/54

CPC classification number: H04L49/901 ,  H04L49/90

Abstract: A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memory between the read and write controllers. The synchronization circuit determines the presence of a stored frame in the random access memory by asynchronously comparing write counter and read counter values stored in gray code counters, where each counter is configured for changing a single bit of a counter value in response to an increment signal. Use of gray code counters enables asynchronous comparisons to be made between the two counter values, independent of the host computer bus clock domain and the network clock domain.

Abstract translation: 网络接口设备包括用作发送和接收缓冲器的随机存取存储器，用于在主计算机总线和分组交换网络之间传输和接收数据帧。 网络接口设备包括用于每个发送和接收缓冲器的读和写控制器，其中每个写控制器在与相应的读控制器分离的时钟域中操作。 存储器管理单元还包括同步电路，其控制仲裁以访问读取和写入控制器之间的随机存取存储器。 同步电路通过异步比较存储在灰度代码计数器中的写入计数器和读取计数器值来确定随机存取存储器中存储的帧的存在，其中每个计数器被配置为响应于增量信号来改变计数器值的单个位 。 使用灰色代码计数器可以在两个计数器值之间进行异步比较，与主机总线时钟域和网络时钟域无关。

公开(公告)号：US06247089B1

公开(公告)日：2001-06-12

申请号：US09154076

申请日：1998-09-16

Applicant: Jerry Chun-Jen Kuo ,  John Chiang

Inventor： Jerry Chun-Jen Kuo ,  John Chiang

IPC: G06F1300

CPC classification number: G06F13/385

Abstract: A network interface has a static random access memory (SRAM) that outputs ordered data to a target by using a first and second holding register, and an output holding register. The SRAM supplies a data set to the first holding register which supplies the first data set to the second holding register. The SRAM also replenishes the first holding register with a second data set. A multiplexer selectively supplies the data set stored in one of the two holding registers to the output holding register which supplies that data set to a bus connected to the target. A bus interface unit state machine supplies a select signal to the multiplexer to control the selection between the first and second holding registers. The state machine generates the select signal based on a bus access controller detecting a target ready signal generated by the target indicating the target's readiness to receive a data set. The select signal enables the multiplexer to supply the next ordered data set to the output holding register. If the target ready signal is asserted too frequently for the first holding register to replenish the second holding register, then the state machine generates a select signal that controls the multiplexer to supply the data set stored within the first holding register to the output holding register. If the target ready signal is asserted relatively infrequently and the first holding register has sufficient time to replenish the second holding register, then the state machine generates a select signal that controls the multiplexer to supply the data set stored within the second holding register to the output holding register.

Abstract translation: 网络接口具有通过使用第一和第二保持寄存器以及输出保持寄存器将有序数据输出到目标的静态随机存取存储器（SRAM）。 SRAM将数据组提供给第一保持寄存器，该第一保持寄存器将第一数据组提供给第二保持寄存器。 SRAM还用第二个数据组补充第一个保持寄存器。 复用器选择性地将存储在两个保持寄存器之一中的数据组提供给输出保持寄存器，该输出保持寄存器将该数据组提供给连接到目标的总线。 总线接口单元状态机向多路复用器提供选择信号以控制第一和第二保持寄存器之间的选择。 状态机基于总线访问控制器产生选择信号，该总线访问控制器检测由目标产生的指示目标准备接收数据集的目标就绪信号。 选择信号使复用器能够将下一个有序数据集提供给输出保持寄存器。 如果对于第一保持寄存器来补偿目标就绪信号太频繁地补充第二保持寄存器，则状态机产生控制多路复用器的选择信号，以将存储在第一保持寄存器内的数据集提供给输出保持寄存器。 如果目标就绪信号相对不频繁地被确定，并且第一保持寄存器具有足够的时间来补充第二保持寄存器，则状态机产生控制多路复用器以将存储在第二保持寄存器内的数据集提供给输出的选择信号 持有登记册。

公开(公告)号：US6161160A

公开(公告)日：2000-12-12

申请号：US146163

申请日：1998-09-03

Applicant: Autumn J. Niu ,  Jerry Chun-Jen Kuo ,  Po-shen Lai

Inventor： Autumn J. Niu ,  Jerry Chun-Jen Kuo ,  Po-shen Lai

IPC: H04L7/02 ,  H04L12/413 ,  H04L12/56 ,  G06F13/36 ,  G06F13/12 ,  G06F15/76 ,  H04L12/54

CPC classification number: H04L12/40032 ,  H04L7/02 ,  H04L12/413 ,  H04L12/56 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9063 ,  H04L49/9089

Abstract: A network interface device includes a random access transmit buffer and a random access receive buffer for transmission and reception of transmission and receive data frames between a host computer bus and a packet switched network. The network interface device includes a memory management unit having read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memories between the read and write controllers. The synchronization circuit asynchronously monitors the amount of data stored in the random access transmit and receive buffer by asynchronously comparing write pointer and read pointer values stored in gray code counters, where each counter is configured for changing a single bit of a counter value in response to an increment signal. A descriptor management unit is used to control DMA reading and writing of transmit data and receive data from and to system memory, respectively, based on descriptor lists, respectively. A pipelining architecture also optimizes transfer of data between the buffers, the PCI bus, and the media access controller.

Abstract translation: 网络接口设备包括随机接入发送缓冲器和用于在主计算机总线与分组交换网络之间发送和接收数据帧的随机接入接收缓冲器。 网络接口设备包括具有用于每个发送和接收缓冲器的读和写控制器的存储器管理单元，其中每个写控制器在与相应的读控制器分离的时钟域中操作。 存储器管理单元还包括同步电路，其控制用于访问读取和写入控制器之间的随机存取存储器的仲裁。 同步电路通过异步地比较存储在灰色代码计数器中的写指针和读指针值异步地监视存储在随机存取发送和接收缓冲器中的数据量，其中每个计数器被配置为响应于 增量信号。 描述符管理单元分别用于分别基于描述符列表来控制DMA读取和写入发送数据并从系统存储器接收数据。 流水线架构还优化了缓冲区，PCI总线和媒体访问控制器之间的数据传输。

公开(公告)号：US6105079A

公开(公告)日：2000-08-15

申请号：US993058

申请日：1997-12-18

Applicant: Jerry Chun-Jen Kuo ,  Po-Shen Lai ,  Autumn Jane Niu

Inventor： Jerry Chun-Jen Kuo ,  Po-Shen Lai ,  Autumn Jane Niu

IPC: G06F13/14 ,  G06F13/24 ,  G06F13/28

CPC classification number: G06F13/24 ,  G06F13/28

Abstract: A network interface device minimizes access latency in initiating a DMA transfer request by selectively supplying a long bit comparison result, generated in a write controller configured for writing data into a buffer memory, directly to a read controller based on a determination that the buffer memory stores less than one complete frame. The media access controller determines the length of the data frame, and supplies the determined length to the write controller. The write controller compares the determined length to a prescribed threshold, and outputs a long bit value for storage in a buffer memory location contiguous with the stored data frame. The long bit can then be used to select a receive buffer threshold optimized for larger frames. If less than one complete frame is stored in the buffer memory, the write controller outputs the long bit information to the read controller, enabling the read controller to initiate a DMA transfer request, using a threshold selected based on the long-bit information, prior to storage of the complete data frame in the buffer memory.

Abstract translation: 网络接口设备通过在配置用于将数据写入缓冲存储器的写入控制器中产生的长比特比较结果基于缓冲存储器存储的确定直接地读取到读取控制器，从而最小化启动DMA传输请求时的访问延迟 少于一个完整的框架。 媒体访问控制器确定数据帧的长度，并将确定的长度提供给写入控制器。 写入控制器将确定的长度与规定的阈值进行比较，并输出用于存储在与存储的数据帧相邻的缓冲存储器位置中的长位值。 然后可以使用长位来选择针对较大帧优化的接收缓冲区阈值。 如果在缓冲存储器中存储少于一个完整的帧，则写控制器将长位信息输出到读控制器，使得读控制器能够使用基于长位信息选择的阈值来发起DMA传送请求 将完整的数据帧存储在缓冲存储器中。

公开(公告)号：US06473818B1

公开(公告)日：2002-10-29

申请号：US09150038

申请日：1998-09-09

Applicant: Autumn J. Niu ,  Po-shen Lai ,  Jerry Chun-Jen Kuo ,  John Chiang

Inventor： Autumn J. Niu ,  Po-shen Lai ,  Jerry Chun-Jen Kuo ,  John Chiang

IPC: G06F1330

CPC classification number: G06F13/387

Abstract: A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. Read and write counters are each implemented as gray code counters that increment a corresponding pointer value by changing a single bit. A synchronization circuit selectively sets a full or empty flag based on an asynchronous comparison of the read and write pointer values. Use of gray code counters for the read pointer value and write pointer value ensures accurate comparisons in a multi-clock environment.

Abstract translation: 网络接口设备包括用作发送和接收缓冲器的随机存取存储器，用于在主计算机总线和分组交换网络之间传输和接收数据帧。 网络接口设备包括用于每个发送和接收缓冲器的读和写控制器，其中每个写控制器在与相应的读控制器分离的时钟域中操作。 读写计数器各自实现为灰度计数器，通过更改单个位来增加对应的指针值。 同步电路基于读取和写入指针值的异步比较选择性地设置完整或空白标志。 对于读指针值和写指针值使用灰色代码计数器可以确保在多时钟环境下的精确比较。

公开(公告)号：US6154796A

公开(公告)日：2000-11-28

申请号：US146168

申请日：1998-09-03

Applicant: Jerry Chun-Jen Kuo ,  Autumn J. Niu ,  Po-Shen Lai

Inventor： Jerry Chun-Jen Kuo ,  Autumn J. Niu ,  Po-Shen Lai

IPC: H04L12/56 ,  G06F13/14 ,  G06F12/00 ,  G06F13/00 ,  H04L12/28

CPC classification number: H04L49/901 ,  H04L49/90 ,  H04L49/9068

Abstract: A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The read and write controllers output status information corresponding to the reading or writing of a stored data frame in the receive buffer. The memory management unit includes a synchronization circuit, which arbitrates updates to the holding registers by the read and write controllers based on the asynchronously determined presence of at least one stored data frame.

Abstract translation: 网络接口设备包括用作发送和接收缓冲器的随机存取存储器，用于在主计算机总线和分组交换网络之间传输和接收数据帧。 网络接口设备包括用于每个发送和接收缓冲器的读和写控制器，其中每个写控制器在与相应的读控制器分离的时钟域中操作。 读取和写入控制器输出与接收缓冲器中存储的数据帧的读取或写入相对应的状态信息。 存储器管理单元包括同步电路，其基于异步确定的至少一个存储的数据帧的存在来仲裁由读取和写入控制器对保持寄存器的更新。

公开(公告)号：US6047001A

公开(公告)日：2000-04-04

申请号：US993056

申请日：1997-12-18

Applicant: Jerry Chun-Jen Kuo ,  Po-Shen Lai ,  Autumn Jane Niu

Inventor： Jerry Chun-Jen Kuo ,  Po-Shen Lai ,  Autumn Jane Niu

IPC: H04L12/56 ,  H04Q11/04 ,  H04L12/28 ,  H04L12/54

CPC classification number: H04Q11/0478 ,  H04L2012/5619 ,  H04L2012/5681

Abstract: A network interface device having a random access memory for buffering data between a host bus interface and a media access controller includes a buffer controller configured for storing a data frame in combination with tracking and status information associated with the storage of the data frame. The memory controller is configured for writing transmit frame data received from a host bus into the random access memory, and generating tracking information based on transfer status signals corresponding to the transfer of the data frame from either a master transfer mode or a slave transfer mode. Hence, the amount of logic associated with generating the tracking, control and/or status information is independent of the nature of the transfer from the host bus. The tracking and status information is stored in memory locations contiguous with the data frame to enable a read controller to access the status information and the corresponding data frame as a single data unit. A second write controller for data received from the media access controller stores the received data frame and the corresponding status information from the media access controller in contiguous memory locations in a receive buffer to form a single data unit.

Abstract translation: 具有用于在主机总线接口和媒体访问控制器之间缓存数据的随机存取存储器的网络接口设备包括：缓冲器控制器，被配置为与跟踪数据帧和与数据帧的存储相关联的状态信息结合存储数据帧。 存储器控制器被配置为将从主机总线接收的发送帧数据写入随机存取存储器，并且基于与主传送模式或从属传输模式的数据帧的传送相对应的传输状态信号来产生跟踪信息。 因此，与生成跟踪，控制和/或状态信息相关联的逻辑量与从主机总线传送的性质无关。 跟踪和状态信息被存储在与数据帧相邻的存储器位置中，以使得读控制器可以将状态信息和对应的数据帧作为单个数据单元访问。 从媒体接入控制器接收的数据的第二写入控制器将接收到的数据帧和来自媒体接入控制器的对应状态信息存储在接收缓冲器中的连续存储器位置中以形成单个数据单元。

公开(公告)号：US06216193B1

公开(公告)日：2001-04-10

申请号：US09146252

申请日：1998-09-03

Applicant: Po-Shen Lai ,  Autumn Jane Niu ,  Jerry Chun-Jen Kuo ,  John M. Chiang

Inventor： Po-Shen Lai ,  Autumn Jane Niu ,  Jerry Chun-Jen Kuo ,  John M. Chiang

IPC: G06F1300

CPC classification number: G06F13/385

Abstract: A network interface includes a multiplexer that selectively supplies either a stored address from an address holding register, or a reload address from a reload address holding register, to a random access buffer memory based on a done delay signal (DMA_DONE_DLY). The done delay signal is generated by an advance signal generator in response to detection of a target initiated termination request on the PCI bus during a DMA data transfer from the random access buffer memory to the target. if the PCI bus transfer is interrupted, the reload address is supplied to the random access buffer memory to enable data output holding registers to be reloaded with the data lost by the target during the interrupted DMA transfer. The array of data output holding registers are capable of recovering from the interrupted PCI bus transfer and output the data set which the target (e.g., the host system memory) expects to receive. The reload address is also supplied to the address register to resume normal addressing by address holding register.

Abstract translation: 网络接口包括多路复用器，其基于完成的延迟信号（DMA_DONE_DLY），将存储的地址从地址保持寄存器或重载地址从重载地址保持寄存器选择性地提供给随机存取缓冲存储器。 响应于在从随机存取缓冲存储器到目标的DMA数据传输期间在PCI总线上检测到目标发起的终止请求，由提前信号发生器产生完成的延迟信号。 如果PCI总线传输中断，则重新加载地址被提供给随机存取缓冲存储器，以使数据输出保持寄存器在DMA中断期间由目标丢失的数据重新加载。 数据输出保持寄存器阵列能够从中断的PCI总线传送恢复，并输出目标（例如，主机系统存储器）期望接收的数据集。 重载地址也提供给地址寄存器，以通过地址保持寄存器恢复正常寻址。