公开(公告)号：US09111645B2

公开(公告)日：2015-08-18

申请号：US13000280

申请日：2009-07-17

Applicant: Kishore Ven Kasamsetty ,  Wayne S. Richardson ,  Kurt Knorpp ,  Frederick A. Ware

Inventor： Kishore Ven Kasamsetty ,  Wayne S. Richardson ,  Kurt Knorpp ,  Frederick A. Ware

IPC: G11C29/56 ,  G11C29/16 ,  G11C29/02 ,  G11C29/12 ,  G11C29/18

CPC classification number: G11C29/16 ,  G11C29/028 ,  G11C29/12015 ,  G11C29/18 ,  G11C29/56012

Abstract: Embodiments of a memory device are described. This memory device includes a signal connector which is electrically coupled to a command/address (CA) link, and an interface circuit, which is electrically coupled to the signal connector, and which receives CA packets via the CA link. A given CA packet includes an address field having address information corresponding to one or more storage locations in the memory device. Moreover, the memory device includes control logic having two operating modes, where, during a first operating mode, the control logic decodes address information in the CA packets using full-field sampling, and, during the second operating mode, the control logic decodes a portion of the address information in the CA packets using sub-field sampling.

Abstract translation: 描述存储器件的实施例。 该存储装置包括电连接到命令/地址（CA）链路的信号连接器和电耦合到信号连接器并且经由CA链路接收CA分组的接口电路。 给定的CA分组包括具有与存储设备中的一个或多个存储位置相对应的地址信息的地址字段。 此外，存储器件包括具有两种操作模式的控制逻辑，其中在第一操作模式期间，控制逻辑使用全场采样来解码CA分组中的地址信息，并且在第二操作模式期间，控制逻辑解码 CA分组中的部分地址信息使用子场采样。

公开(公告)号：US20050248383A1

公开(公告)日：2005-11-10

申请号：US11123225

申请日：2005-05-06

Applicant: Wayne Fang ,  Wayne Richardson ,  Kurt Knorpp

Inventor： Wayne Fang ,  Wayne Richardson ,  Kurt Knorpp

IPC: H03B1/00 ,  H03K3/00 ,  H03K17/693

CPC classification number: H03K17/693

Abstract: A pulse multiplexed output subsystem is disclosed. In one particular exemplary embodiment, the output subsystem may comprise a plurality of pulse generators, a first pair of transistors, and a second pair of transistors, wherein each of the first pair of transistors is coupled to a respective one of a first pair of the plurality of pulse generators, and wherein each of the second pair of transistors is coupled to a respective one of a second pair of the plurality of pulse generators. The output subsystem may also comprise a first pair of resistive loads, wherein each of the first pair of resistive loads is coupled to a respective one of the first pair of transistors and a respective one of the second pair of transistors, and a first current source coupled to the first pair of transistors and the second pair of transistors.

Abstract translation: 公开了脉冲多路复用输出子系统。 在一个特定示例性实施例中，输出子系统可以包括多个脉冲发生器，第一对晶体管和第二对晶体管，其中第一对晶体管中的每一个耦合到第一对晶体管中的相应一个 多个脉冲发生器，并且其中第二对晶体管中的每一个耦合到第二对多个脉冲发生器中的相应一个。 输出子系统还可以包括第一对电阻负载，其中第一对电阻负载中的每一个耦合到第一对晶体管中的相应一个和第二对晶体管中的相应一个，以及第一电流源 耦合到第一对晶体管和第二对晶体管。