公开(公告)号：US20110202725A1

公开(公告)日：2011-08-18

申请号：US12708376

申请日：2010-02-18

Applicant: John R. Rose ,  Lawrence A. Spracklen ,  Zoran Radovic

Inventor： John R. Rose ,  Lawrence A. Spracklen ,  Zoran Radovic

IPC: G06F12/02 ,  G06F12/08

CPC classification number: G06F9/30021 ,  G06F9/30018

Abstract: A method and processor supporting architected instructions for tracking and determining set membership, such as by implementing Bloom filters. The apparatus includes storage arrays (e.g., registers) and an execution core configured to store an indication that a given value is a member of a set, including by executing an architected instruction having an operand specifying the given value, wherein executing comprises hashing applying a hash function to the value to determine an index into one of the storage arrays and setting a bit of the storage array corresponding to the index. An architected query instruction is later executed to determine if a query value is not a member of the set, including by applying the hash function to the query value to determine an index into the storage array and determining whether a bit at the index of the storage array is set.

Abstract translation: 支持用于跟踪和确定集合成员资格的架构化指令的方法和处理器，例如通过实现Bloom过滤器。 该装置包括存储阵列（例如，寄存器）和被配置为存储给定值是组的成员的指示的执行核心，包括通过执行具有指定给定值的操作数的架构化指令，其中执行包括哈希应用 将hash函数的值确定为一个索引到一个存储阵列中，并设置一个与索引相对应的存储阵列。 稍后执行架构化查询指令以确定查询值是否不是该集合的成员，包括通过将哈希函数应用于查询值来确定存储阵列中的索引并确定存储器的索引处的位 数组被设置。

公开(公告)号：US20110185150A1

公开(公告)日：2011-07-28

申请号：US12693634

申请日：2010-01-26

Applicant: Lawrence A. Spracklen

Inventor： Lawrence A. Spracklen

IPC: G06F15/80 ,  G06F9/02

CPC classification number: G06F9/30032 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30101

Abstract: Systems and methods for performing single instruction multiple data (SIMD) operations on a data set. The methods may include examining a structure of the data set to determine what reorganization may be necessary to facilitate SIMD processing. The method may include selecting a stored bit mask corresponding to the organization of the data set and loading the bit mask into an application specific register (ASR). Subsequently, the data may be reorganized inline according to the ASR as the data is loaded into the SIMD functional unit such that the SIMD functional unit may operate on the data set. The results of the SIMD operation may be written to a results register.

Abstract translation: 对数据集执行单指令多数据（SIMD）操作的系统和方法。 这些方法可以包括检查数据集的结构以确定促进SIMD处理可能需要什么重组。 该方法可以包括选择与数据组的组织相对应的存储的位掩码，并将位掩码加载到专用寄存器（ASR）中。 随后，随着数据被加载到SIMD功能单元中，可以根据ASR在线重新组织数据，使得SIMD功能单元可以对数据集进行操作。 SIMD操作的结果可以写入结果寄存器。

公开(公告)号：US20100250964A1

公开(公告)日：2010-09-30

申请号：US12414831

申请日：2009-03-31

Applicant: Christopher H. Olson ,  Gregory F. Grohoski ,  Lawrence A. Spracklen

Inventor： Christopher H. Olson ,  Gregory F. Grohoski ,  Lawrence A. Spracklen

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30003 ,  G06F9/30007 ,  G06F9/30018 ,  G06F9/30167 ,  G06F9/382 ,  G06F9/3851 ,  G06F9/3877 ,  H04L9/0625 ,  H04L2209/122 ,  H04L2209/125 ,  H04L2209/24

Abstract: A processor including instruction support for implementing the Camellia block cipher algorithm may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include one or more Camellia instructions defined within the ISA. In addition, the Camellia instructions may be executable by the cryptographic unit to implement portions of a Camellia cipher that is compliant with Internet Engineering Task Force (IETF) Request For Comments (RFC) 3713. In response to receiving a Camellia F( )-operation instruction defined within the ISA, the cryptographic unit may perform an F( ) operation, as defined by the Camellia cipher, upon a data input operand and a subkey operand, in which the data input operand and subkey operand may be specified by the Camellia F( )-operation instruction.

Abstract translation: 包括用于实现Camellia块密码算法的指令支持的处理器可以从定义的指令集体系结构（ISA）发出用于执行编程器可选择指令的执行。 处理器可以包括可以接收执行指令的密码单元。 说明书包括在ISA内定义的一个或多个Camellia指令。 另外，山茶花指令可以由加密单元执行，以实现符合因特网工程任务组（IETF）请求注释（RFC）3713的Camellia密码的部分。响应于接收到Camellia F（）操作 在ISA内定义的指令中，加密单元可以在数据输入操作数和子键操作数上执行由Camellia密码定义的F（）操作，其中数据输入操作数和子键操作数可以由Camellia F （）操作指令。

公开(公告)号：US07373482B1

公开(公告)日：2008-05-13

申请号：US11139708

申请日：2005-05-26

Applicant: Lawrence A. Spracklen ,  Yuan C. Chou ,  Santosh G. Abraham

Inventor： Lawrence A. Spracklen ,  Yuan C. Chou ,  Santosh G. Abraham

IPC: G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC classification number: G06F9/3842 ,  G06F9/30043 ,  G06F9/30105 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/383 ,  G06F9/3838 ,  G06F9/3863

Abstract: One embodiment of the present invention provides a system that improves the effectiveness of prefetching during execution of instructions in scout mode. During operation, the system executes program instructions in a normal-execution mode. Upon encountering a condition which causes the processor to enter scout mode, the system performs a checkpoint and commences execution of instructions in scout mode, wherein the instructions are speculatively executed to prefetch future memory operations, but wherein results are not committed to the architectural state of a processor. During execution of a load instruction during scout mode, if the load instruction is a special load instruction and if the load instruction causes a lower-level cache miss, the system waits for data to be returned from a higher-level cache before resuming execution of subsequent instructions in scout mode, instead of disregarding the result of the load instruction and immediately resuming execution in scout mode. In this way, the data returned from the higher-level cache can help in generating addresses for subsequent prefetches during scout mode.

Abstract translation: 本发明的一个实施例提供了一种提高在侦察模式下执行指令期间预取的有效性的系统。 在运行期间，系统以正常执行模式执行程序指令。 当遇到导致处理器进入侦察模式的情况时，系统执行检查点并开始执行侦察模式中的指令，其中推测性地执行指令以预取将来的存储器操作，但是其中结果未被提交到建筑状态 一个处理器 在侦察模式期间执行加载指令期间，如果加载指令是特殊加载指令，如果加载指令导致较低级别的高速缓存未命中，则系统等待从更高级别的缓存返回数据，然后恢复执行 随后在侦察模式下的指令，而不是忽略加载指令的结果，并立即恢复执行侦察模式。 以这种方式，从高级缓存返回的数据可以帮助在侦察模式期间为后续预取生成地址。

公开(公告)号：US07013377B2

公开(公告)日：2006-03-14

申请号：US10654256

申请日：2003-09-03

Applicant: Lawrence A. Spracklen ,  Stevan Vlaovic ,  Steven R. Hart

Inventor： Lawrence A. Spracklen ,  Stevan Vlaovic ,  Steven R. Hart

IPC: G06F12/02

CPC classification number: G06F9/30127 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/30101

Abstract: A method and apparatus provides the capability for a single function to safely use multiple register windows within the same function, with minimal additional support from the operating system, by specifying a new window pointer, the “Effective Current Window Pointer” (ECWP), to be used in conjunction with the prior art window pointer. According to the present invention, the new window pointer ECWP can be used to override the prior art window pointer in dictating from which register window the operands stipulated by the instructions to be executed are sourced/sinked. Consequently, using the method and apparatus of the invention, the number of spills to memory is reduced, the number of instructions required is decreased, resources are used more efficiently, and costly dependency problems and RAW (read-after-write) stalls are prevented.

Abstract translation: 一种方法和装置通过指定一个新的窗口指针“有效当前窗口指针”（ECWP），为单个功能提供了在相同功能中安全地使用多个寄存器窗口的能力，同时通过操作系统的最小额外的支持， 与现有技术的窗口指针结合使用。 根据本发明，可以使用新的窗口指针ECWP来覆盖现有技术的窗口指针，从而从哪个寄存器窗口指定要执行的指令规定的操作数来源/汇入。 因此，使用本发明的方法和装置，减少了对存储器的溢出次数，减少了所需指令的数量，更有效地使用资源，并且防止了昂贵的依赖问题和RAW（写后读取）停止 。

公开(公告)号：US5960012A

公开(公告)日：1999-09-28

申请号：US877720

申请日：1997-06-23

Applicant: Lawrence A. Spracklen

Inventor： Lawrence A. Spracklen

IPC: G06F11/10 ,  H03M13/00

CPC classification number: G06F11/10

Abstract: A method for improved speed performance in calculating a checksum by loading groups of data elements into first and second registers. The loaded data elements are then added in parallel, with each data element being added to its corresponding data element in the other register. Thus, multiple additions can be done in parallel, with the result being added to a cumulative result and the process repeated.

Abstract translation: 一种用于通过将数据元素组加载到第一和第二寄存器来计算校验和来提高速度性能的方法。 然后并行地加载加载的数据元素，每个数据元素被添加到其他寄存器中的相应数据元素。 因此，可以并行地进行多次添加，结果被添加到累积结果中，并且重复该过程。

公开(公告)号：US09317286B2

公开(公告)日：2016-04-19

申请号：US12414831

申请日：2009-03-31

Applicant: Christopher H. Olson ,  Gregory F. Grohoski ,  Lawrence A. Spracklen

Inventor： Christopher H. Olson ,  Gregory F. Grohoski ,  Lawrence A. Spracklen

IPC: G06F9/30 ,  G06F9/38 ,  H04L9/06 ,  G06F15/00

CPC classification number: G06F9/30145 ,  G06F9/30003 ,  G06F9/30007 ,  G06F9/30018 ,  G06F9/30167 ,  G06F9/382 ,  G06F9/3851 ,  G06F9/3877 ,  H04L9/0625 ,  H04L2209/122 ,  H04L2209/125 ,  H04L2209/24

Abstract: A processor including instruction support for implementing the Camellia block cipher algorithm may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include one or more Camellia instructions defined within the ISA. In addition, the Camellia instructions may be executable by the cryptographic unit to implement portions of a Camellia cipher that is compliant with Internet Engineering Task Force (IETF) Request For Comments (RFC) 3713. In response to receiving a Camellia F( )-operation instruction defined within the ISA, the cryptographic unit may perform an F( ) operation, as defined by the Camellia cipher, upon a data input operand and a subkey operand, in which the data input operand and subkey operand may be specified by the Camellia F( )-operation instruction.

Abstract translation: 包括用于实现Camellia块密码算法的指令支持的处理器可以从定义的指令集体系结构（ISA）发出用于执行编程器可选择指令的执行。 处理器可以包括可以接收执行指令的密码单元。 说明书包括在ISA内定义的一个或多个Camellia指令。 另外，山茶花指令可以由加密单元执行，以实现符合因特网工程任务组（IETF）请求注释（RFC）3713的Camellia密码的部分。响应于接收到Camellia F（）操作 在ISA内定义的指令中，加密单元可以在数据输入操作数和子键操作数上执行由Camellia密码定义的F（）操作，其中数据输入操作数和子键操作数可以由Camellia F （）操作指令。

公开(公告)号：US08732437B2

公开(公告)日：2014-05-20

申请号：US12693634

申请日：2010-01-26

Applicant: Lawrence A. Spracklen

Inventor： Lawrence A. Spracklen

IPC: G06F15/00 ,  G06F15/76

CPC classification number: G06F9/30032 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30101

Abstract: Systems and methods for performing single instruction multiple data (SIMD) operations on a data set. The methods may include examining a structure of the data set to determine what reorganization may be necessary to facilitate SIMD processing. The method may include selecting a stored bit mask corresponding to the organization of the data set and loading the bit mask into an application specific register (ASR). Subsequently, the data may be reorganized inline according to the ASR as the data is loaded into the SIMD functional unit such that the SIMD functional unit may operate on the data set. The results of the SIMD operation may be written to a results register.

Abstract translation: 对数据集执行单指令多数据（SIMD）操作的系统和方法。 这些方法可以包括检查数据集的结构以确定促进SIMD处理可能需要什么重组。 该方法可以包括选择与数据组的组织相对应的存储的位掩码，并将位掩码加载到专用寄存器（ASR）中。 随后，随着数据被加载到SIMD功能单元中，可以根据ASR在线重新组织数据，使得SIMD功能单元可以对数据集进行操作。 SIMD操作的结果可以写入结果寄存器。

公开(公告)号：US07827383B2

公开(公告)日：2010-11-02

申请号：US11684358

申请日：2007-03-09

Applicant: Lawrence A. Spracklen ,  Santosh G. Abraham ,  Adam R. Talcott

Inventor： Lawrence A. Spracklen ,  Santosh G. Abraham ,  Adam R. Talcott

IPC: G06F9/34 ,  G06F12/08

CPC classification number: G06F12/1027 ,  G06F12/1036 ,  G06F2212/1024 ,  G06F2212/683

Abstract: In one embodiment, a processor comprises execution circuitry and a translation lookaside buffer (TLB) coupled to the execution circuitry. The execution circuitry is configured to execute a store instruction having a data operand; and the execution circuitry is configured to generate a virtual address as part of executing the store instruction. The TLB is coupled to receive the virtual address and configured to translate the virtual address to a first physical address. Additionally, the TLB is coupled to receive the data operand and to translate the data operand to a second physical address. A hardware accelerator is also contemplated in various embodiments, as is a processor coupled to the hardware accelerator, a method, and a computer readable medium storing instruction which, when executed, implement a portion of the method.

Abstract translation: 在一个实施例中，处理器包括耦合到执行电路的执行电路和转换后备缓冲器（TLB）。 执行电路被配置为执行具有数据操作数的存储指令; 并且所述执行电路被配置为生成作为执行所述存储指令的一部分的虚拟地址。 所述TLB被耦合以接收所述虚拟地址并被配置为将所述虚拟地址转换为第一物理地址。 此外，TLB被耦合以接收数据操作数并将数据操作数转换为第二物理地址。 还可以在各种实施例中考虑硬件加速器，以及耦合到硬件加速器的处理器，方法和存储指令的计算机可读介质，其在被执行时实现该方法的一部分。

公开(公告)号：US20100246815A1

公开(公告)日：2010-09-30

申请号：US12414871

申请日：2009-03-31

Applicant: Christopher H. Olson ,  Gregory F. Grohoski ,  Lawrence A. Spracklen

Inventor： Christopher H. Olson ,  Gregory F. Grohoski ,  Lawrence A. Spracklen

IPC: H04L9/28 ,  G06F9/30 ,  G06F9/312

CPC classification number: G09C1/00 ,  G06F7/483 ,  G06F7/722 ,  G06F9/30007 ,  G06F9/30018 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/382 ,  G06F9/3851 ,  G06F9/3877 ,  H04L9/0625 ,  H04L9/0631 ,  H04L2209/12 ,  H04L2209/24

Abstract: A processor including instruction support for implementing the Kasumi block cipher algorithm may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include one or more Kasumi instructions defined within the ISA. In addition, the Kasumi instructions may be executable by the cryptographic unit to implement portions of a Kasumi cipher that is compliant with 3rd Generation Partnership Project (3GPP) Technical Specification TS 35.202 version 8.0.0. In response to receiving a Kasumi FL( )-operation instruction defined within the ISA, the cryptographic unit may perform an FL( ) operation, as defined by the Kasumi cipher, upon a data input operand and a subkey operand in which the data input operand and subkey operand may be specified by the Kasumi FL( )-operation instruction.

Abstract translation: 包括用于实现Kasumi块密码算法的指令支持的处理器可以从定义的指令集体系结构（ISA）发出用于执行编程器可选择指令的执行。 处理器可以包括可以接收执行指令的密码单元。 说明包括在ISA内定义的一个或多个Kasumi指令。 此外，Kasumi指令可以由密码单元执行，以实现符合第三代合作伙伴计划（3GPP）技术规范TS 35.202版本8.0.0的Kasumi密码的部分。 响应于接收到在ISA内定义的Kasumi FL（）操作指令，加密单元可以对数据输入操作数和数据输入操作数的子键操作数执行如Kasumi密码所定义的FL（）操作 并且子键操作数可以由Kasumi FL（）操作指令指定。