公开(公告)号：US20150296006A1

公开(公告)日：2015-10-15

申请号：US14251360

申请日：2014-04-11

Applicant: MAXELER TECHNOLOGIES LTD.

Inventor： Oliver PELL ,  Peter SANDERS ,  Nicolas Norvez

IPC: H04L29/08 ,  G06F9/50

CPC classification number: H04L67/1006 ,  G06F9/4806 ,  G06F9/5005 ,  G06F9/5044 ,  G06F9/5077 ,  G06F2209/5022 ,  H04L67/1025 ,  H04L67/1036

Abstract: A system and method of dynamically provisioning virtualised computational resources in a networked computer architecture includes at least one client device operable to run one or more client applications, at least one server device and a resource controller. Each server device comprises one or more physical processors with local memory. Each server device provides a virtual resource layer through which one or more virtual processing resources can be defined and through which the physical processors of the server device can be assigned to the virtual processing resources. In use, one or more virtual processing resources is assigned to a client application for processing of data processing workloads. The resource controller then monitors the utilisation of each virtual processing resource and/or any physical processor assigned to the virtual processing resource. The resource controller can dynamically adjust which, and how many, physical processors are assigned to the virtual processing resource.

Abstract translation: 在联网的计算机体系结构中动态地配置虚拟计算资源的系统和方法包括至少一个可操作以运行一个或多个客户端应用，至少一个服务器设备和资源控制器的客户端设备。 每个服务器设备包括具有本地存储器的一个或多个物理处理器。 每个服务器设备提供虚拟资源层，通过该虚拟资源层可以定义一个或多个虚拟处理资源，通过该虚拟资源层可以将服务器设备的物理处理器分配给虚拟处理资源。 在使用中，将一个或多个虚拟处理资源分配给用于处理数据处理工作负载的客户端应用程序。 资源控制器然后监视分配给虚拟处理资源的每个虚拟处理资源和/或任何物理处理器的利用率。 资源控制器可以动态地调整分配给虚拟处理资源的物理处理器和数量。

公开(公告)号：US20140167987A1

公开(公告)日：2014-06-19

申请号：US13717188

申请日：2012-12-17

Applicant: MAXELER TECHNOLOGIES LTD.

Inventor： Oliver PELL ,  Stephen GIRDLESTONE ,  Henning MEYER

IPC: H03M5/14

CPC classification number: H03M5/145 ,  H03M7/30 ,  H03M7/46 ,  H03M7/6023 ,  H03M7/6029

Abstract: A method of data compression includes obtaining a data set comprising a sequence of data blocks comprising a predetermined number of data items, partitioning said data set into one or more groups each comprising a predetermined number of data blocks, and performing data compression on one or more groups of data blocks. Data compression is performed by associating a control data item with each of said blocks, generating a control vector comprising the control data items assigned to each of said blocks within a group, removing data blocks comprising entirely data items having said specified value, compressing data blocks comprising at least one data item having a value different from said specified value using a fixed-rate compression scheme, providing a compressed data stream comprising said compressed data blocks, and providing an associated control vector stream to enable control of said compressed data stream.

Abstract translation: 一种数据压缩方法包括获得包括包括预定数量的数据项的数据块序列的数据集，将所述数据集划分为一个或多个组，每个组包括预定数量的数据块，并且对一个或多个数据进行数据压缩 数据块组。 通过将控制数据项与每个所述块相关联来执行数据压缩，产生包括分配给组内的每个所述块的控制数据项的控制向量，去除包含完全具有所述指定值的数据项的数据块，压缩数据块 包括使用固定速率压缩方案具有不同于所述指定值的值的至少一个数据项，提供包括所述压缩数据块的压缩数据流，以及提供关联的控制向量流以使得能够控制所述压缩数据流。

公开(公告)号：US08689156B2

公开(公告)日：2014-04-01

申请号：US13779457

申请日：2013-02-27

Applicant: Maxeler Technologies Ltd.

Inventor： James Huggett ,  Jacob Alexis Bower ,  Oliver Pell

IPC: G06F17/50

CPC classification number: G06F9/30079 ,  G06F17/5054

Abstract: A method of generating a hardware design for a pipelined parallel stream processor. The method includes defining a processing operation designating processes to be implemented in hardware as part of said pipelined parallel stream processor and defining a graph representing said processing operation as a parallel structure in the time domain as a function of clock cycles. The method also includes defining the at least one data path and associated latencies of said graph as a set of algebraic linear inequalities, collectively solving the set of linear inequalities for the entire graph, optimizing the at least one data path in the graph using the solved linear inequalities to produce an optimized graph, and utilizing the optimized graph to define an optimized hardware design for implementation in hardware as the pipelined parallel stream processor.

Abstract translation: 一种为流水线并行流处理器生成硬件设计的方法。 该方法包括定义处理操作，指定要在硬件中实现的处理，作为所述流水线并行流处理器的一部分，并且将表示所述处理操作的图形定义为时域中的并行结构，作为时钟周期的函数。 该方法还包括将所述图形的至少一个数据路径和相关联的延迟定义为一组代数线性不等式，共同地解决整个图形的线性不等式集合，使用求解的图来优化图中的至少一个数据路径 线性不等式以产生优化的图，并且利用优化的图来定义用于在硬件中实现的优化的硬件设计作为流水线并行流处理器。

公开(公告)号：US08671371B1

公开(公告)日：2014-03-11

申请号：US13683722

申请日：2012-11-21

Applicant: Maxeler Technologies Ltd.

Inventor： Robert Gwilym Dimond

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F2217/68

Abstract: A method of utilizing high level synthesis to automatically configure control logic of a hardware design for a pipelined parallel stream processor includes obtaining a scheduled graph representing a processing operation in the time domain as a function of clock cycles. The graph comprises a data path to be implemented in hardware as part of said stream processor, an input, an output, and parallel branches to enable data values to be streamed therethrough from the input to the output as a function of increasing clock cycle. The data path is partitioned to divide it into a plurality of discrete regions. Discrete control logic elements are assigned to each region using high level synthesis. The graph and assigned control logic is used to define a hardware design for the pipelined parallel stream processor.

Abstract translation: 利用高级合成来自动配置流水线并行流处理器的硬件设计的控制逻辑的方法包括获取表示时域中的处理操作的调度图，作为时钟周期的函数。 该图包括作为所述流处理器的一部分在硬件中实现的数据路径，输入，输出和并行分支，以使数据值能够作为增加时钟周期的函数从输入流输出到输出。 将数据路径分割成多个离散区域。 使用高级合成将离散控制逻辑元件分配给每个区域。 图形和分配的控制逻辑用于定义流水线并行流处理器的硬件设计。

公开(公告)号：US20130173890A1

公开(公告)日：2013-07-04

申请号：US13779457

申请日：2013-02-27

Applicant: MAXELER TECHNOLOGIES LTD.

Inventor： James HUGGETT ,  Jacob Alexis BOWER ,  Oliver PELL

IPC: G06F9/30

CPC classification number: G06F9/30079 ,  G06F17/5054

Abstract: A method of generating a hardware design for a stream processor. The method includes defining a graph representing a processing operation designating processes to be implemented in hardware as part of the stream processor. The graph represents the processing operation in the time domain as a function of clock cycles and includes at least one data path. At least one stream offset object is provided located at a particular point in the data path. The stream offset object is operable to access, for a particular clock cycle and for the particular point in the data path, data values from a clock cycle different from the particular clock cycle

Abstract translation: 一种为流处理器生成硬件设计的方法。 该方法包括定义表示处理操作的图，其指定要在硬件中实现的流程，作为流处理器的一部分。 该图表示时域中的处理操作，作为时钟周期的函数，并且包括至少一个数据路径。 提供位于数据路径中的特定点处的至少一个流偏移对象。 流偏移对象可操作用于访问特定时钟周期和数据路径中的特定点，来自不同于特定时钟周期的时钟周期的数据值