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公开(公告)号：US08289063B2
公开(公告)日：2012-10-16
申请号：US13110439
申请日：2011-05-18
IPC分类号： H03K3/013
CPC分类号： G06F1/10 , H04L7/0012
摘要： Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.
摘要翻译： 这里公开了一种数字系统，其包括具有携带参考时钟的路径和沿着路径设置的可调延迟元件的分配网络，以及耦合到分配网络以接收参考时钟并被配置为被驱动的第一和第二时钟域 通过各自的时钟波形，每个时钟波形具有与参考时钟共同的频率。 所述数字系统还包括耦合到所述第一和第二时钟域的相位检测器，以基于所述时钟波形产生相位差信号;以及控制电路，耦合到所述相位检测器并被配置为基于所述相位差来调节所述可调节延迟元件 信号。
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公开(公告)号：US07956664B2
公开(公告)日：2011-06-07
申请号：US11949673
申请日：2007-12-03
IPC分类号： H03K3/00
CPC分类号： G06F1/10 , H04L7/0012
摘要： Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.
摘要翻译： 这里公开了一种数字系统，其包括具有携带参考时钟的路径和沿着路径设置的可调节延迟元件的分配网络，以及耦合到分配网络以接收参考时钟并被配置为被驱动的第一和第二时钟域 通过各自的时钟波形，每个时钟波形具有与参考时钟共同的频率。 所述数字系统还包括耦合到所述第一和第二时钟域的相位检测器，以基于所述时钟波形产生相位差信号;以及控制电路，耦合到所述相位检测器并且被配置为基于所述相位差调节所述可调节延迟元件 信号。
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13.发明申请RESONANT CLOCK DISTRIBUTION NETWORK ARCHITECTURE FOR TRACKING PARAMETER VARIATIONS IN CONVENTIONAL CLOCK DISTRIBUTION NETWORKS 有权用于跟踪常规时钟分配网络中的参数变化的共享时钟分配网络架构公开(公告)号：US20110084775A1
公开(公告)日：2011-04-14
申请号：US12903188
申请日：2010-10-12
IPC分类号： H03B5/12
摘要： A resonant clock distribution network architecture is proposed that enables a resonant clock network to track the impact of parameter variations on the insertion delay of a conventional clock distribution network, thus limiting clock skew between the two networks and yielding increased performance. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
摘要翻译： 提出了一种谐振时钟分配网络架构，其使得谐振时钟网络能够跟踪参数变化对传统时钟分配网络的插入延迟的影响，从而限制两个网络之间的时钟偏移并产生增加的性能。 这种网络通常适用于具有各种时钟频率的半导体器件，以及诸如微处理器，ASIC和SOC的高性能和低功耗时钟要求。
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公开(公告)号：US20110084773A1
公开(公告)日：2011-04-14
申请号：US12903172
申请日：2010-10-12
IPC分类号： H03B5/12
摘要： A resonant clock distribution network architecture is proposed that is capable of single-step operation through the use of selective control in the resonant clock drivers and the deployment of flip-flops that require the clock to remain stable for a sufficiently long time between any two consecutive state updates. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
摘要翻译： 提出了一种谐振时钟分配网络架构，其能够通过在谐振时钟驱动器中使用选择性控制和触发器的部署来进行单步操作，其需要时钟在任何两个连续的时间之间保持稳定足够长的时间 状态更新。 这种网络通常适用于具有各种时钟频率的半导体器件，以及诸如微处理器，ASIC和SOC的高性能和低功耗时钟要求。
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公开(公告)号：US20080303552A1
公开(公告)日：2008-12-11
申请号：US11949664
申请日：2007-12-03
CPC分类号： G06F1/10 , H04L7/0012
摘要： Disclosed herein is a digital system that includes a distribution network to carry a reference clock and a plurality of circuit domains coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. Each circuit domain of the plurality of circuit domains includes a respective clock generator driven by the reference clock to generate a resonant clock signal, respective circuitry coupled to the clock generator to operate in accordance with the resonant clock signal, with the circuitry including a capacitive load for the resonant clock signal and a respective inductance coupled to the circuitry and the clock generator to resonate the capacitive load of the circuitry.
摘要翻译： 这里公开了一种数字系统，其包括分配网络以携带参考时钟和耦合到分配网络的多个电路域，以根据参考时钟接收用于同步操作的参考时钟。 多个电路域的每个电路域包括由参考时钟驱动以产生谐振时钟信号的相应时钟发生器，相应的电路耦合到时钟发生器以根据谐振时钟信号进行操作，电路包括容性负载 用于谐振时钟信号和耦合到电路和时钟发生器的相应电感器以谐振电路的容性负载。
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公开(公告)号：US20080150605A1
公开(公告)日：2008-06-26
申请号：US11949673
申请日：2007-12-03
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , H04L7/0012
摘要： Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.
摘要翻译： 这里公开了一种数字系统，其包括具有携带参考时钟的路径和沿着路径设置的可调延迟元件的分配网络，以及耦合到分配网络以接收参考时钟并被配置为被驱动的第一和第二时钟域 通过各自的时钟波形，每个时钟波形具有与参考时钟共同的频率。 所述数字系统还包括耦合到所述第一和第二时钟域的相位检测器，以基于所述时钟波形产生相位差信号;以及控制电路，耦合到所述相位检测器并被配置为基于所述相位差来调节所述可调节延迟元件 信号。
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17.发明授权公开(公告)号：US08502569B2
公开(公告)日：2013-08-06
申请号：US12903174
申请日：2010-10-12
IPC分类号： H03B1/00
摘要： An architecture for resonant clock distribution networks is proposed. The proposed architecture allows for the energy-efficient operation of the resonant clock distribution network in conventional mode, so that it meets target specifications for the clock waveform. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to at-speed testing and to binning of semiconductor devices according to achievable performance levels.
摘要翻译： 提出了谐振时钟分配网络的架构。 所提出的架构允许在常规模式下谐振时钟分配网络的能量效率操作，使得它满足时钟波形的目标规范。 这种架构通常适用于具有多个时钟频率的半导体器件，以及诸如微处理器，ASIC和SOC的高性能和低功耗时钟要求。 此外，它可应用于根据可实现的性能水平进行半速度测试和二进制分组。
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18.发明授权Resonant clock and interconnect architecture for digital devices with multiple clock networks 有权具有多个时钟网络的数字设备的谐振时钟和互连架构公开(公告)号：US08461873B2
公开(公告)日：2013-06-11
申请号：US13103985
申请日：2011-05-09
IPC分类号： H03K19/096
CPC分类号： G06F1/10
摘要： A clock and data distribution network is proposed that distributes clock and data signals without buffers, thus achieving very low jitter, skew, loose timing requirements, and energy consumption. Such network uses resonant drivers and is generally applicable to architectures for programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs), as well as other semiconductor devices with multiple clock networks operating at various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, applications specific integrated circuits (ASICs), and Systems-on-a-Chip (SOCs).
摘要翻译： 提出了一种时钟和数据分配网络，无需缓冲器分配时钟和数据信号，从而实现非常低的抖动，偏移，松动的时序要求和能耗。 这种网络使用谐振驱动器，并且通常可应用于诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）的架构，以及具有以各种时钟频率工作的多个时钟网络的其他半导体器件，以及高性能和低 功率时钟要求，如微处理器，专用集成电路（ASIC）和片上系统（SOC）。
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公开(公告)号：US08362811B2
公开(公告)日：2013-01-29
申请号：US12903172
申请日：2010-10-12
IPC分类号： H03B1/00
摘要： A resonant clock distribution network architecture is proposed that is capable of single-step operation through the use of selective control in the resonant clock drivers and the deployment of flip-flops that require the clock to remain stable for a sufficiently long time between any two consecutive state updates. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
摘要翻译： 提出了一种谐振时钟分配网络架构，其能够通过在谐振时钟驱动器中使用选择性控制和触发器的部署来进行单步操作，其需要时钟在任何两个连续的时间之间保持稳定足够长的时间 状态更新。 这种网络通常适用于具有各种时钟频率的半导体器件，以及诸如微处理器，ASIC和SOC的高性能和低功耗时钟要求。
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20.发明授权Method for selecting natural frequency in resonant clock distribution networks with no inductor overhead 有权在没有电感开销的谐振时钟分配网络中选择固有频率的方法公开(公告)号：US08339209B2
公开(公告)日：2012-12-25
申请号：US12903163
申请日：2010-10-12
摘要： An inductor architecture for resonant clock distribution networks is described. This architecture allows for the adjustment of the natural frequency of a resonant clock distribution network, so that it achieves energy-efficient operation at multiple clock frequencies. The proposed architecture exhibits no inductor overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.
摘要翻译： 描述了谐振时钟分配网络的电感结构。 该架构允许调整谐振时钟分配网络的固有频率，从而在多个时钟频率下实现能量效率的操作。 所提出的架构没有显示电感开销。 这种架构通常适用于具有多个时钟频率的半导体器件，以及诸如微处理器，ASIC和SOC的高性能和低功耗时钟要求。 此外，它可应用于根据可实现的性能水平对半导体器件进行合并。
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