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1.发明申请RESONANT CLOCK AND INTERCONNECT ARCHITECTURE FOR DIGITAL DEVICES WITH MULTIPLE CLOCK NETWORKS 有权具有多个时钟网络的数字设备的谐振时钟和互连结构公开(公告)号：US20090027085A1
公开(公告)日：2009-01-29
申请号：US12125009
申请日：2008-05-21
CPC分类号： G06F1/10
摘要： A clock and data distribution network is proposed that distributes clock and data signals without buffers, thus achieving very low jitter, skew, loose timing requirements, and energy consumption. Such network uses resonant drivers and is generally applicable to architectures for programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs), as well as other semiconductor devices with multiple clock networks operating at various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, applications specific integrated circuits (ASICs), and Systems-on-a-Chip (SOCs).
摘要翻译： 提出了一种时钟和数据分配网络，无需缓冲器分配时钟和数据信号，从而实现非常低的抖动，偏移，松动的时序要求和能耗。 这种网络使用谐振驱动器，并且通常可应用于诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）的架构，以及具有以各种时钟频率工作的多个时钟网络的其他半导体器件，以及高性能和低 功率时钟要求，如微处理器，专用集成电路（ASIC）和片上系统（SOC）。
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公开(公告)号：US06879190B2
公开(公告)日：2005-04-12
申请号：US10406367
申请日：2003-04-03
IPC分类号： G11C7/12 , G11C11/408 , G11C11/4094 , G11C11/417 , G11C11/418 , G11C11/419 , H03K17/00 , H03K17/687 , H03B1/00
CPC分类号： G11C11/4094 , G11C7/12 , G11C11/4085 , G11C11/417 , G11C11/418 , G11C11/419
摘要： The present invention provides an energy recovering driver that includes a pull-up control, a pull-down control and a transmission gate. The pull up control is responsive to a pull-up control signal and a clock signal to turn the transmission gate ON and OFF and predetermined positions of the clock signal. The pull-down control is responsive to a pull-down control signal and the clock signal to turn the transmission gate ON and OFF at other predetermined locations of the clock signal. The transmission gate transmits the clock signal when at an ON condition and does not transmit the clock signal when in an OFF condition.
摘要翻译： 本发明提供一种能量回收驱动器，其包括上拉控制，下拉控制和传输门。 上拉控制响应于上拉控制信号和时钟信号以使传输门接通和断开以及时钟信号的预定位置。 下拉控制响应于下拉控制信号和时钟信号，以在时钟信号的其它预定位置处打开和关闭传输门。 传输门在处于ON状态时发送时钟信号，并且在处于OFF状态时不发送时钟信号。
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公开(公告)号：US08593183B2
公开(公告)日：2013-11-26
申请号：US12903158
申请日：2010-10-12
IPC分类号： H03K3/00
摘要： An architecture for controlling the clock waveform characteristics, including but not limited to the clock amplitude and clock rise and/or fall times, of resonant clock distribution networks is proposed. This architecture relies on controlling the size of clock drivers and the duty cycles of reference clocks. It is targeted at resonant clock distribution networks and allows for the adjustment of resonant clock waveform characteristics with no need to route an additional power grid. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
摘要翻译： 提出了一种用于控制时钟波形特性的架构，包括但不限于谐振时钟分配网络的时钟振幅和时钟上升和/或下降时间。 该架构依赖于控制时钟驱动器的大小和参考时钟的占空比。 它的目标是谐振时钟分配网络，并允许调整谐振时钟波形特性，而无需路由额外的电网。 这种架构通常适用于具有多个时钟频率的半导体器件，以及诸如微处理器，ASIC和SOC的高性能和低功耗时钟要求。
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4.发明申请Resonant Clock And Interconnect Architecture For Digital Devices With Multiple Clock Networks 有权具有多个时钟网络的数字设备的谐振时钟和互连架构公开(公告)号：US20110210761A1
公开(公告)日：2011-09-01
申请号：US13103985
申请日：2011-05-09
IPC分类号： H03K19/096
CPC分类号： G06F1/10
摘要： A clock and data distribution network is proposed that distributes clock and data signals without buffers, thus achieving very low jitter, skew, loose timing requirements, and energy consumption. Such network uses resonant drivers and is generally applicable to architectures for programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs), as well as other semiconductor devices with multiple clock networks operating at various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, applications specific integrated circuits (ASICs), and Systems-on-a-Chip (SOCs).
摘要翻译： 提出了一种时钟和数据分配网络，无需缓冲器分配时钟和数据信号，从而实现非常低的抖动，偏移，松动的时序要求和能耗。 这种网络使用谐振驱动器，并且通常可应用于诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）的架构，以及具有以各种时钟频率工作的多个时钟网络的其他半导体器件，以及高性能和低 功率时钟要求，如微处理器，专用集成电路（ASIC）和片上系统（SOC）。
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5.发明申请公开(公告)号：US20110090019A1
公开(公告)日：2011-04-21
申请号：US12903168
申请日：2010-10-12
IPC分类号： H03B5/12
摘要： An architecture for resonant clock distribution networks is proposed. This architecture allows for the energy-efficient operation of a resonant clock distribution network at multiple clock frequencies through the deployment of flip-flops that can be selectively enabled. The proposed architecture is primarily targeted at the design of resonant clock networks with integrated inductors and exhibits no inductor overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.
摘要翻译： 提出了谐振时钟分配网络的架构。 该架构允许通过部署可以选择性地启用的触发器来实现在多个时钟频率下的谐振时钟分配网络的能量效率的操作。 所提出的架构主要针对具有集成电感器的谐振时钟网络的设计，并且没有显示电感器开销。 这种架构通常适用于具有多个时钟频率的半导体器件，以及诸如微处理器，ASIC和SOC的高性能和低功耗时钟要求。 此外，它可应用于根据可实现的性能水平对半导体器件进行合并。
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公开(公告)号：US20110084736A1
公开(公告)日：2011-04-14
申请号：US12903158
申请日：2010-10-12
IPC分类号： H03K3/00
摘要： An architecture for controlling the clock waveform characteristics, including but not limited to the clock amplitude and clock rise and/or fall times, of resonant clock distribution networks is proposed. This architecture relies on controlling the size of clock drivers and the duty cycles of reference clocks. It is targeted at resonant clock distribution networks and allows for the adjustment of resonant clock waveform characteristics with no need to route an additional power grid. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
摘要翻译： 提出了一种用于控制时钟波形特性的架构，包括但不限于谐振时钟分配网络的时钟振幅和时钟上升和/或下降时间。 该架构依赖于控制时钟驱动器的大小和参考时钟的占空比。 它的目标是谐振时钟分配网络，并允许调整谐振时钟波形特性，而无需路由额外的电网。 这种架构通常适用于具有多个时钟频率的半导体器件，以及诸如微处理器，ASIC和SOC的高性能和低功耗时钟要求。
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公开(公告)号：US07719317B2
公开(公告)日：2010-05-18
申请号：US11949669
申请日：2007-12-03
CPC分类号： G06F1/10 , H04L7/0012
摘要： Disclosed herein is a digital system that includes a distribution network to carry a reference clock, and a circuit domain coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. The circuit domain includes a clock generator driven by the reference clock to generate a resonant clock signal, an input port to receive a control signal, and a gate coupled to the input port to discontinue application of the resonant clock signal within the circuit domain based on the control signal.
摘要翻译： 这里公开了一种数字系统，其包括用于承载参考时钟的分配网络，以及耦合到分配网络的电路域，以根据参考时钟接收用于同步操作的参考时钟。 电路域包括由参考时钟驱动以产生谐振时钟信号的时钟发生器，用于接收控制信号的输入端口和耦合到输入端口的栅极，以基于电路域中断谐振时钟信号在电路域内的应用 控制信号。
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公开(公告)号：US07355454B2
公开(公告)日：2008-04-08
申请号：US11153135
申请日：2005-06-15
IPC分类号： H03K19/094 , H03K19/0175
CPC分类号： H03K19/0019 , H02M3/158
摘要： A boost circuit is disclosed that includes a plurality of transistors connected between complementary phases of a clock signal. The boost circuit further includes a first electrical node connected between at least two of the plurality of transistors wherein the plurality of transistors are configured to generate a second voltage from a first voltage at the electrical node in response to the clock signal.
摘要翻译： 公开了一种升压电路，其包括连接在时钟信号的互补相位之间的多个晶体管。 升压电路还包括连接在所述多个晶体管中的至少两个晶体管之间的第一电节点，其中所述多个晶体管被配置为响应于所述时钟信号从所述电节点处的第一电压产生第二电压。
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9.发明授权公开(公告)号：US08659338B2
公开(公告)日：2014-02-25
申请号：US12903154
申请日：2010-10-12
摘要： A resonant clock distribution network architecture is proposed that uses clock drivers of programmable size and reference clocks of programmable duty cycle to achieve a target clock rise time and clock amplitude with low energy consumption when operating in any one of multiple clock frequencies in resonant or non-resonant mode. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
摘要翻译： 提出了一种谐振时钟分配网络架构，其使用可编程大小的时钟驱动器和可编程占空比的参考时钟来实现目标时钟上升时间和具有低能耗的时钟振幅，当在谐振或非谐振时钟的多个时钟频率中工作时， 谐振模式。 这种网络通常适用于具有各种时钟频率的半导体器件，以及诸如微处理器，ASIC和SOC的高性能和低功耗时钟要求。
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10.发明授权Architecture for frequency-scaled operation in resonant clock distribution networks 有权谐振时钟分配网络中频率规模运算的架构公开(公告)号：US08400192B2
公开(公告)日：2013-03-19
申请号：US12903168
申请日：2010-10-12
IPC分类号： H03B1/00
摘要： An architecture for resonant clock distribution networks is proposed. This architecture allows for the energy-efficient operation of a resonant clock distribution network at multiple clock frequencies through the deployment of flip-flops that can be selectively enabled. The proposed architecture is primarily targeted at the design of resonant clock networks with integrated inductors and exhibits no inductor overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.
摘要翻译： 提出了谐振时钟分配网络的架构。 该架构允许通过部署可以选择性地启用的触发器来实现在多个时钟频率下的谐振时钟分配网络的能量效率的操作。 所提出的架构主要针对具有集成电感器的谐振时钟网络的设计，并且没有显示电感器开销。 这种架构通常适用于具有多个时钟频率的半导体器件，以及诸如微处理器，ASIC和SOC的高性能和低功耗时钟要求。 此外，它可应用于根据可实现的性能水平对半导体器件进行合并。
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