公开(公告)号：US07317800B1

公开(公告)日：2008-01-08

申请号：US10030521

申请日：2000-05-26

Applicant: Matthias Vierthaler ,  Martin Winterer

Inventor： Matthias Vierthaler ,  Martin Winterer

IPC: H03G3/00 ,  H03G5/00

CPC classification number: H03G5/165

Abstract: A circuit for processing an input audio signal received at an input of the circuit provides a processed audio signal at a circuit output. The circuit includes first and second conductive paths through which the received audio signal travels. The audio signal is processed such that harmonics of the signal components with a low-frequency are generated in the second path and are admixed to the signal in the first path. In the second path the audio signal is sequentially bandpass filtered, weighted with a correction factor, amplified, limited to a predetermined value, and bandpass filtered, where the correction factor is reduced when the predetermined value is exceeded.

Abstract translation: 用于处理在电路的输入处接收的输入音频信号的电路在电路输出处提供经处理的音频信号。 电路包括接收到的音频信号通过的第一和第二导电路径。 处理音频信号，使得在第二路径中产生具有低频的信号分量的谐波并且与第一路径中的信号相混合。 在第二路径中，音频信号被顺序带通滤波，用校正因子进行加权，被放大，限制为预定值，并进行带通滤波，其中当超过预定值时校正因子减小。

公开(公告)号：US06492913B2

公开(公告)日：2002-12-10

申请号：US09932473

申请日：2001-08-17

Applicant: Matthias Vierthaler ,  Martin Winterer ,  Stefan Mueller ,  Thomas Hilpert ,  Carsten Noeske

Inventor： Matthias Vierthaler ,  Martin Winterer ,  Stefan Mueller ,  Thomas Hilpert ,  Carsten Noeske

IPC: H03M700

CPC classification number: H04N5/607 ,  H04N5/602 ,  H04N21/42607 ,  H04N21/8106

Abstract: An integrated circuit for decoding an analog audio signal includes a tuner that receives the analog audio signal and provides a sound intercarrier frequency signal. A digital demodulator receives and digitizes the sound intercarrier frequency signal to provide a digitized sound intercarrier frequency signal, and digitally demodulates the digitized sound intercarrier frequency signal to provide a digitized multichannel television sound (MTS) demodulated signal. A digital broadcast television system committee (BTSC) compatible decoder receives and decodes the digitized multichannel television sound (MTS) demodulated signal, and provides a summed (L+R) audio output signal and a difference (L−R) audio output signal.

Abstract translation: 用于解码模拟音频信号的集成电路包括接收模拟音频信号并提供声音载波间频率信号的调谐器。 数字解调器接收和数字化声音载波间频率信号，以提供数字化的声音载波间频率信号，并且数字解调数字化的载波间频率信号以提供数字化的多声道电视声音（MTS）解调信号。 数字广播电视系统委员会（BTSC）兼容解码器接收并解码数字化的多声道电视声音（MTS）解调信号，并提供加和（L + R）音频输出信号和差分（L-R）音频输出信号。

公开(公告)号：US6122381A

公开(公告)日：2000-09-19

申请号：US854922

申请日：1997-05-13

Applicant: Martin Winterer

Inventor： Martin Winterer

IPC: H04R3/00 ,  G10K15/12 ,  H04R3/12 ,  H04S3/00 ,  H04S5/02 ,  H04R5/00

CPC classification number: H04S3/00 ,  H04S2400/01

Abstract: A stereophonic sound system is disclosed, having a source of stereophonic signals which contain a right signal and a left signal as well as further signals which supplement the right and left signals to convey a three-dimensional sound impression. The right and left signals are adapted to a stereo base of a pair of loudspeakers having a correspondingly small size by means of a modification circuit. Of the stereophonic signals, only the right and left signals are fed to the modification circuit so that they are falsified as little as possible. An improved system for conveying a three-dimensional sound impression is thus provided.

Abstract translation: 公开了一种立体声系统，其具有包含右信号和左信号的立体声信号源，以及补充左和右信号以传达三维声音印象的其它信号。 右和左信号通过修改电路适应于具有相应较小尺寸的一对扬声器的立体声基座。 在立体声信号中，只有右和左信号被馈送到修改电路，使得它们被尽可能少地伪造。 因此提供了用于传送三维声音印象的改进的系统。

公开(公告)号：US5898604A

公开(公告)日：1999-04-27

申请号：US928575

申请日：1997-09-12

Applicant: Martin Winterer

Inventor： Martin Winterer

IPC: G06F7/52 ,  G06F7/50

CPC classification number: G06F7/5324

Abstract: The invention relates to a digital signal processor with a RAM (random-access memory) having its output connected to a first input and, through a first temporary storage device to a second input of a multiplier, with an adder following the multiplier, and with a clock device for controlling data-word transfers. The speed of the processor is increased by connecting a second auxiliary storage device between the RAM and the first input of the multiplier and providing a first switching element via which the RAM and the second temporary storage device are connectable to the first input of the multiplier.

Abstract translation: 本发明涉及一种具有RAM（随机存取存储器）的数字信号处理器，其RAM的输出连接到第一输入端，并且通过第一临时存储装置连接到乘法器的第二输入端，与乘法器之后的加法器，以及与 用于控制数据字传输的时钟设备。 通过在RAM和乘法器的第一输入之间连接第二辅助存储设备来提供处理器的速度，并提供第一开关元件，通过该第一开关元件，RAM和第二临时存储设备可连接到乘法器的第一输入。

公开(公告)号：US5181115A

公开(公告)日：1993-01-19

申请号：US718740

申请日：1991-06-21

Applicant: Peter Flamm ,  Martin Winterer ,  Hans-Juergen Desor

Inventor： Peter Flamm ,  Martin Winterer ,  Hans-Juergen Desor

IPC: H03L7/06 ,  H03L7/099 ,  H04N5/12 ,  H04N9/87 ,  H04N9/89

CPC classification number: H03L7/0994 ,  H04N9/87

Abstract: A digital phase-locked loop has a periodically overflowing digital oscillator (DCO), implemented as a modulo adder, and a processor device. The processor device adjusts the period T of the digital oscillator to a nominal period, determined from periodically occurring synchronizing pulses, by comparing the actual phase of the digital oscillator with a set phase at the control clock rate of the periodic synchronizing pulses. After the digital oscillator has been locked to the nominal period, the processor device compares the phases by using a double-frequency signal sequence of one-half line period derived from the digital oscillator output signal. The DCO output signal is fed to a correction device where an address-phase signal, locked to the DCO output signal, is generated so that when a non-periodic synchronizing pulse occurs, the address-phase signal is shifted by one period of the signal sequence of one-half line period with respect to the digital oscillator output signal.

Abstract translation: 数字锁相环具有作为模加法器实现的周期性溢出数字振荡器（DCO）和处理器装置。 处理器设备通过将数字振荡器的实际相位与周期性同步脉冲的控制时钟速率下的设定相位相比较，将数字振荡器的周期T调整到从周期性发生的同步脉冲确定的标称周期。 在数字振荡器被锁定到标称周期之后，处理器设备通过使用从数字振荡器输出信号导出的半行时间段的双频信号序列来比较相位。 DCO输出信号被馈送到校正装置，其中产生锁定到DCO输出信号的地址相位信号，使得当发生非周期同步脉冲时，地址相位信号被移位一个信号周期 相对于数字振荡器输出信号的一半行周期的序列。

公开(公告)号：US5057796A

公开(公告)日：1991-10-15

申请号：US610634

申请日：1990-11-08

Applicant: Martin Winterer

Inventor： Martin Winterer

IPC: G11B20/06 ,  H01L27/12 ,  H03C3/00

CPC classification number: H03C3/00

Abstract: In a frequency modulation system, a modulating signal is split into its low-frequency and high-frequency components. The low frequency component is used to modulate a carrier signal by conventional means in a first circuit and the low- and high-frequency components are used to narrowband modulate the carrier signal in a second circuit. The outputs of the first and second circuits are combined to provide a frequency modulated signal. The modulating and carrier signals can be binary-coded signals.

Abstract translation: 在频率调制系统中，调制信号被分为低频和高频分量。 低频分量用于通过第一电路中的常规装置来调制载波信号，并且低频和高频分量用于在第二电路中对载波信号进行窄带调制。 第一和第二电路的输出被组合以提供调频信号。 调制和载波信号可以是二进制编码信号。