公开(公告)号：US5062004A

公开(公告)日：1991-10-29

申请号：US307124

申请日：1989-02-06

Applicant: Martin Winterer ,  Hans-Jurgen Desor

Inventor： Martin Winterer ,  Hans-Jurgen Desor

IPC: H04N9/804 ,  H04N9/79 ,  H04N9/808 ,  H04N9/83

CPC classification number: H04N9/79 ,  H04N9/83 ,  H04N9/831

Abstract: An improved digital video signal processing circuit, for common use in the recording and playback modes of a video tape recorder, has a chrominance processing circuit for processing the chrominance signal of the input digital composite video signal through a first baseband mixer, a chrominance processor, and a second baseband mixer, and a luminance processing circuit for frequency modulating/demodulating the luminance signal, so that the processed chrominance and luminance signals can be added together to form an output digital composite video signal. The improved digital circuit automatically regulates the frequencies of the mixing signals for both mixers using line stepping signals obtained from a horizontal line sweep generator in the luminance processing circuit. The possibility of phase errors is eliminated, and quadrature errors in the chrominance signal are prevented.

Abstract translation: 一种改进的数字视频信号处理电路，用于在录像机的记录和重放模式中常用的具有色度处理电路，用于通过第一基带混频器，色度处理器处理输入的数字复合视频信号的色度信号， 以及第二基带混频器，以及用于对亮度信号进行频率调制/解调的亮度处理电路，使得经处理的色度和亮度信号可以相加在一起以形成输出的数字复合视频信号。 改进的数字电路使用在亮度处理电路中从水平线扫描发生器获得的线路步进信号自动调节两个混频器的混频信号的频率。 消除了相位误差的可能性，并且防止了色度信号中的正交误差。

公开(公告)号：US4872129A

公开(公告)日：1989-10-03

申请号：US272968

申请日：1988-11-18

Applicant: Heinrich Pfeifer ,  Werner Reich ,  Martin Winterer

Inventor： Heinrich Pfeifer ,  Werner Reich ,  Martin Winterer

IPC: H03M3/00 ,  H03H17/00 ,  H03H17/02 ,  H03H17/04 ,  H03H17/06

CPC classification number: H03H17/0671 ,  H03H17/0657

Abstract: To realize the transfer function in a digital filter circuit:H(z)=b(1-z.sup.-kn)(1-z.sup.-n).sup.m-1 /(1-z.sup.-).sup.m,the following sections are cascaded: a multiplier for multiplying by 2.sup.-q ; m-1 integrators, each including a delay element which provides a delay equal to the period of the input sampling frequency; and mth integrator including a delay element which is reset by the output sampling clock; a sampling device which is switched at the output sampling clock rate; m-2 differentiators, each including a delay element which provides a delay equal to the period of the output sampling clock; and an (m-1)st differentiator including k delay elements which each provide a delay equal to the period of the output sampling clock.

Abstract translation: 为了实现数字滤波器电路中的传递函数：H（z）= b（1-z-kn）（1-zn）m-1 /（1-z-）m，以下部分级联： 乘以2-q; m-1个积分器，每个均包括提供等于输入采样频率周期的延迟的延迟元件; 第m个积分器包括由输出采样时钟复位的延迟元件; 以输出采样时钟速率切换的采样装置; m-2微分器，每个差分器包括提供等于输出采样时钟周期的延迟的延迟元件; 以及包括k个延迟元件的第（m-1）个微分器，每个延迟元件提供等于输出采样时钟周期的延迟。

公开(公告)号：US5226088A

公开(公告)日：1993-07-06

申请号：US677073

申请日：1991-03-29

Applicant: Martin Winterer ,  Dieter Baecher

Inventor： Martin Winterer ,  Dieter Baecher

IPC: H04B1/10 ,  H04H20/88

CPC classification number: H04B1/1036

Abstract: Method and apparatus for active noise suppression in stereo multiplex signals particularly in an automotive radio receiver includes an insertion circuit where the disturbed signal section is replaced with an insertion signal formed by sampled signal values/signal sections which are located before and/or after the disturbed signal section. Basic-delay stages ensure that only those sample values are used for the insertion signal which are separated from the respective instant of insertion by a time interval having an integral relationship nT to the period T of a carrier contained in the stereo multiplex signal (where n is a positive integer).

Abstract translation: 立体声多路复用信号中的有源噪声抑制方法和装置特别是在汽车无线电接收机中包括一个插入电路，其中干扰的信号部分由被置于干扰之前和/或之后的采样信号值/信号部分形成的插入信号所代替 信号部分。 基本延迟阶段确保只有这些采样值被用于插入信号，该插入信号与相应的插入时间间隔具有与立体声多路复用信号中所包含的载波的周期T的积分关系nT的时间间隔（其中n 是正整数）。

公开(公告)号：US06351631B1

公开(公告)日：2002-02-26

申请号：US09249524

申请日：1999-02-12

Applicant: Carsten Noeske ,  Martin Winterer

Inventor： Carsten Noeske ,  Martin Winterer

IPC: G08C2504

CPC classification number: H04N5/607 ,  H03L7/081 ,  H03L7/0994 ,  H03L7/10 ,  H04H40/18 ,  H04H2201/13

Abstract: Carrier generation facility for a switchable digital demodulator (D) of digital MPX signals (mpx1) with associated pilot signal (p1) which are locked to an arbitrary clock signal (t1). A pilot signal PLL (10) generates a first carrier signal (x1.1, x2.1) and a second carrier signal (x1.2) by means of a first value allocator (15) and a second value allocator (20), respectively. According to the MPX signal (mpx1) to be demodulated, a control device (60) delivers a start value (i0) and at least one phase correction value (k1, k2). The start value (i0) sets the capture range of the pilot signal PLL (10) for the pilot signal (p1) according to the respective standard. In a first correcting device (16) and/or a second correcting device (23), the phase correction values (k1, k2) correct the system-inherent phase deviations of the first carrier signal (x1.1, x2.1) and/or the second carrier signal (x1.2).

Abstract translation: 具有锁定到任意时钟信号（t1）的关联导频信号（p1）的数字MPX信号（mpx1）的可切换数字解调器（D）的载波生成设备。 导频信号PLL（10）通过第一值分配器（15）和第二值分配器（20）产生第一载波信号（x1.1，x2.1）和第二载波信号（x1.2） 分别。 根据要解调的MPX信号（mpx1），控制装置（60）传送开始值（i0）和至少一个相位校正值（k1，k2）。 起始值（i0）根据各自的标准设定导频信号（p1）的导频信号PLL（10）的捕获范围。 在第一校正装置（16）和/或第二校正装置（23）中，相位校正值（k1，k2）校正第一载波信号（x1.1，x2.1）的系统固有相位偏差 /或第二载波信号（x1.2）。

公开(公告)号：US06281813B1

公开(公告)日：2001-08-28

申请号：US09349594

申请日：1999-07-09

Applicant: Matthias Vierthaler ,  Martin Winterer ,  Stefan Mueller ,  Thomas Hilpert ,  Carsten Noeske

Inventor： Matthias Vierthaler ,  Martin Winterer ,  Stefan Mueller ,  Thomas Hilpert ,  Carsten Noeske

IPC: H04N560

CPC classification number: H04N5/607 ,  H04N5/602 ,  H04N21/42607 ,  H04N21/8106

Abstract: An integrated circuit for decoding an analog audio signal includes a tuner that receives the analog audio signal and provides a sound intercarrier frequency signal. A digital demodulator receives and digitizes the sound intercarrier frequency signal to provide a digitized sound intercarrier frequency signal, and digitally demodulates the digitized sound intercarrier frequency signal to provide a digitized multichannel television sound (MTS) demodulated signal. A digital broadcast television system committee (BTSC) compatible decoder receives and decodes the digitized multichannel television sound (MTS) demodulated signal, and provides a summed (L+R) audio output signal and a difference (L−R) audio output signal.

Abstract translation: 用于解码模拟音频信号的集成电路包括接收模拟音频信号并提供声音载波间频率信号的调谐器。 数字解调器接收和数字化声音载波间频率信号，以提供数字化的声音载波间频率信号，并且数字解调数字化的载波间频率信号以提供数字化的多声道电视声音（MTS）解调信号。 数字广播电视系统委员会（BTSC）兼容解码器接收并解码数字化的多声道电视声音（MTS）解调信号，并提供加和（L + R）音频输出信号和差分（L-R）音频输出信号。

公开(公告)号：US07162038B1

公开(公告)日：2007-01-09

申请号：US09357006

申请日：1999-07-19

Applicant: Martin Winterer ,  Stefan Mueller ,  Thomas Hilpert

Inventor： Martin Winterer ,  Stefan Mueller ,  Thomas Hilpert

IPC: H04H5/00 ,  H04H3/00

CPC classification number: H04N5/60 ,  H04N5/46 ,  H04N21/4622 ,  H04N21/8106

Abstract: Audio source selection circuit (QW) for an audio signal processor with inputs for source signals (F1, F2, NA, NB) provided by at least one source (Q1, Q2), with a processing device (V) which forms pairs of signals from the source signals, with a settable source selection logic (Qs) to which the channels of the processing device (V) are applied, and with outputs coupled to signal outputs of the settable source selection logic (Qs) and each forming an output channel (Co1, Co2, Co3), the processing device (V) including an automatic audio mode setting device which generates suitable intermediate channels (Cz1, Cz2, Cz3, Cz4) from the source signals (F1, F2, NA, NB) according to a source- and application-related mode.

Abstract translation: 用于具有由至少一个源（Q 1，Q 2）提供的源信号（F 1，F 2，NA，NB）的输入的音频信号处理器的音频源选择电路（QW）与处理装置（V） 使用来自源信号的信号对，以及施加处理装置（V）的通道的可设置的源选择逻辑（Qs），以及耦合到可设置源选择逻辑（Qs）的信号输出和每个 形成输出通道（Co 1，Co 2，Co 3），所述处理装置（V）包括从源信号产生合适的中间通道（Cz 1，Cz 2，Cz 3，Cz 4）的自动音频模式设定装置 （F 1，F 2，NA，NB）根据源和应用相关模式。

公开(公告)号：US6141646A

公开(公告)日：2000-10-31

申请号：US61465

申请日：1998-04-16

Applicant: Martin Winterer ,  Miodrag Temerinac

Inventor： Martin Winterer ,  Miodrag Temerinac

IPC: G10L13/00 ,  G10K15/00 ,  H04H20/00 ,  H04S1/00 ,  G10K15/04

CPC classification number: H04S1/007 ,  H04H2201/13

Abstract: A digital sound processor for processing multiple standard sound signals and including an audio source which is connected to a digital control input of the sound processor and generates, via externally or internally applied control signals, an audible signal or an audible signal sequence which is fed via the output devices of the sound processor to reproducers.

Abstract translation: 一种用于处理多个标准声音信号并包括连接到声音处理器的数字控制输入的音频源并经由外部或内部施加的控制信号产生可听信号或可听信号序列的数字声音处理器， 声音处理器的输出设备再现。

公开(公告)号：US5822437A

公开(公告)日：1998-10-13

申请号：US754144

申请日：1996-11-22

Applicant: Martin Winterer

Inventor： Martin Winterer

IPC: H04S1/00 ,  H04R5/00

CPC classification number: H04S1/002

Abstract: A circuit is disclosed for modifying a first signal and a second signal from a signal source providing at least two signals. The circuit including devices for forming signal components from the first and second signals. The signal components are then combined into a modified first signal and a modified second signal by means of a first combining device and a second combining device, respectively.

Abstract translation: 公开了一种用于修改来自提供至少两个信号的信号源的第一信号和第二信号的电路。 该电路包括用于从第一和第二信号形成信号分量的装置。 然后，信号分量通过第一组合装置和第二组合装置分别组合成经修改的第一信号和修改的第二信号。

公开(公告)号：US5717618A

公开(公告)日：1998-02-10

申请号：US509517

申请日：1995-07-31

Applicant: Andreas Menkhoff ,  Miodrag Temerinac ,  Franz-Otto Witte ,  Martin Winterer

Inventor： Andreas Menkhoff ,  Miodrag Temerinac ,  Franz-Otto Witte ,  Martin Winterer

IPC: H03H17/00 ,  H03H17/06 ,  G06F17/17

CPC classification number: H03H17/028 ,  H03H17/0642

Abstract: An improved method for digital interpolation of signals for a second interpolation filter is disclosed which permits a high signal/noise ratio with a minimum amount of circuitry for an overall system comprising first and second interpolation filters. The method for digital interpolation of signals requires multiplying delayed input values locked to a first signal by corresponding weighting factors which are dependent on a time-difference value determined by the interpolating instant and the time grid of the first clock signal. The weighting factors are determined by an impulse response in the time domain. The associated transfer function has an attenuation characteristic in the frequency domain which, with respect to the stop bands, is limited essentially to the alias regions located at the frequency multiples of the first clock signal. Each of these alias regions is assigned at least two adjacent zeros, or in the presence of double-order zeros, at least one of the alias regions and the associated periodic alias regions are assigned at least one further zero of the transfer function.

Abstract translation: 公开了用于第二内插滤波器的信号的数字插值的改进方法，其允许具有包括第一和第二内插滤波器的整个系统的最小量的电路的高信噪比。 用于信号的数字插值的方法需要将锁定到第一信号的延迟输入值乘以相应的加权因子，这些相应的加权因子取决于由内插时刻和第一时钟信号的时间网格确定的时间差值。 加权因子由时域中的脉冲响应决定。 相关联的传递函数在频域中具有衰减特性，其相对于阻带，基本上限于位于第一时钟信号的倍频的别名区域。 这些别名区域中的每一个被分配至少两个相邻的零，或者在存在双重零的情况下，至少一个别名区域和相关联的周期性别名区域被分配至少一个传递函数的另一个零。

公开(公告)号：US4964046A

公开(公告)日：1990-10-16

申请号：US453027

申请日：1989-12-22

Applicant: Soenke Mehrgardt ,  Martin Winterer

Inventor： Soenke Mehrgardt ,  Martin Winterer

IPC: G06F17/10

CPC classification number: G06F17/10

Abstract: A central processor for digital signal processing operates at a high clock rate. In the central processor, data is transferred and processed largely in parallel and simultaneously. A buffer is inserted in the data link between a data memory and an ALU by means of at least three data buses so that within one clock period, all necessary data transfers for a two-address operation of the ALU are performed by using the buffer. In particular, a unidirectional data bus and a bidirectional data bus transfer data from the buffer to the ALU, and the bidirectional data bus transfers the result of an ALU operation back to the buffer. Simultaneously with the transfers between the buffer and the ALU, a data transfer is performed between the data memory and the buffer. The data transfers and the data processing are controlled by a control unit in which a fixed program is stored segment by segment. The use of pipelining in the control unit permits a high processing speed. The use of delayed branching is supplemented by the skip technique. The central processor does not utilize interrupt control. Rather, a scheduler selectively changes the sequence in which a program operates in response to an external or internal task request only at the end of the segment currently being executed so that the current program segment is concluded without interruption.

Abstract translation: 用于数字信号处理的中央处理器以高时钟速率工作。 在中央处理器中，数据被大量并行和同时传送和处理。 缓冲器通过至少三个数据总线插入在数据存储器和ALU之间的数据链路中，使得在一个时钟周期内，通过使用缓冲器来执行用于ALU的双地址操作的所有必要数据传输。 特别地，单向数据总线和双向数据总线将数据从缓冲器传送到ALU，并且双向数据总线将ALU操作的结果传送回缓冲器。 与缓冲器和ALU之间的传输同时进行数据存储器和缓冲器之间的数据传输。 数据传输和数据处理由其中固定程序逐段存储的控制单元控制。 在控制单元中使用流水线可以实现高处理速度。 延迟分支的使用由跳过技术补充。 中央处理器不使用中断控制。 相反，调度器仅在当前正在执行的段的结尾响应于外部或内部任务请求选择性地改变程序运行的序列，使得当前程序段被不中断地结束。