公开(公告)号：US08149874B2

公开(公告)日：2012-04-03

申请号：US13110217

申请日：2011-05-18

Applicant: Michael Ching ,  Steven Woo

Inventor： Michael Ching ,  Steven Woo

IPC: H04J3/16

CPC classification number: G06F13/4072 ,  H04L5/14 ,  H04L5/143 ,  H04L5/18 ,  H04L25/0272 ,  H04L25/0294 ,  Y02D10/14 ,  Y02D10/151

Abstract: Apparatus and methods allocate I/O bandwidth of an electrical component, such as an IC, by configuring an I/O interface into various types of interfaces. In an embodiment of the present invention, an I/O interface is configured into either a bi-directional contact, unidirectional contact (including either a dedicated transmit or dedicated receive contact) or a maintenance contact used in a maintenance or calibration mode of operation. The I/O interface is periodically reconfigured to optimally allocate I/O bandwidth responsive to system parameters, such as changing data workloads in the electronic components. System parameters include, but are not limited to, 1) number of transmit-receive bus turnarounds; 2) number of transmit and/or receive data packets; 3) user selectable setting 4) number of transmit and/or receive commands; 5) direct requests from one or more electronic components; 6) number of queued transactions in one or more electronic components; 7) transmit burst-length setting, 8) duration or cycle count of bus commands, and control strobes such as address/data strobe, write enable, chip select, data valid, data ready; 9) power and/or temperature of one or more electrical components; 10) information from executable instructions, such as a software application or operating system; 11) multiple statistics over respective periods of time to determine if using a different bandwidth allocation would result in better performance. The importance of a system parameter may be weighted over time in an embodiment of the present invention.

Abstract translation: 装置和方法通过将I / O接口配置成各种类型的接口来分配诸如IC的电气部件的I / O带宽。 在本发明的实施例中，I / O接口被配置为双向接触，单向接触（包括专用发射或专用接收接点）或在维护或校准操作模式中使用的维护接点。 周期性地重新配置I / O接口，以响应于系统参数（例如改变电子组件中的数据工作负载）来最佳地分配I / O带宽。 系统参数包括但不限于：1）发送接收总线周转数; 2）发送和/或接收数据包的数量; 3）用户可选设置4）发送和/或接收命令的数量; 5）一个或多个电子元件的直接请求; 6）一个或多个电子组件中的排队交易数; 7）发送突发长度设置，8）总线命令的持续时间或周期计数，以及控制选通，如地址/数据选通，写使能，片选，数据有效，数据准备; 9）一个或多个电气部件的功率和/或温度; 10）来自可执行指令的信息，例如软件应用或操作系统; 11）在各个时间段内的多个统计，以确定是否使用不同的带宽分配将导致更好的性能。 在本发明的实施例中，系统参数的重要性可以随时间加权。

公开(公告)号：US08073009B2

公开(公告)日：2011-12-06

申请号：US12177747

申请日：2008-07-22

Applicant: Michael Ching ,  Steven Woo

Inventor： Michael Ching ,  Steven Woo

IPC: H04J3/16

CPC classification number: G06F13/4072 ,  H04L5/14 ,  H04L5/143 ,  H04L5/18 ,  H04L25/0272 ,  H04L25/0294 ,  Y02D10/14 ,  Y02D10/151

Abstract: Apparatus and methods allocate I/O bandwidth of an electrical component, such as an IC, by configuring an I/O interface into various types of interfaces. In an embodiment of the present invention, an I/O interface is configured into either a bi-directional contact, unidirectional contact (including either a dedicated transmit or dedicated receive contact) or a maintenance contact used in a maintenance or calibration mode of operation. The I/O interface is periodically reconfigured to optimally allocate I/O bandwidth responsive to system parameters, such as changing data workloads in the electronic components. System parameters include, but are not limited to, 1) number of transmit-receive bus turnarounds; 2) number of transmit and/or receive data packets; 3) user selectable setting 4) number of transmit and/or receive commands; 5) direct requests from one or more electronic components; 6) number of queued transactions in one or more electronic components; 7) transmit burst-length setting, 8) duration or cycle count of bus commands, and control strobes such as address/data strobe, write enable, chip select, data valid, data ready; 9) power and/or temperature of one or more electrical components; 10) information from executable instructions, such as a software application or operating system; 11) multiple statistics over respective periods of time to determine if using a different bandwidth allocation would result in better performance. The importance of a system parameter may be weighted over time in an embodiment of the present invention.

Abstract translation: 装置和方法通过将I / O接口配置成各种类型的接口来分配诸如IC的电气部件的I / O带宽。 在本发明的实施例中，I / O接口被配置为双向接触，单向接触（包括专用发射或专用接收接点）或在维护或校准操作模式中使用的维护接点。 周期性地重新配置I / O接口，以响应于系统参数（例如改变电子组件中的数据工作负载）来最佳地分配I / O带宽。 系统参数包括但不限于：1）发送接收总线周转数; 2）发送和/或接收数据包的数量; 3）用户可选设置4）发送和/或接收命令的数量; 5）一个或多个电子元件的直接请求; 6）一个或多个电子组件中的排队交易数; 7）发送突发长度设置，8）总线命令的持续时间或周期计数，以及控制选通，如地址/数据选通，写使能，片选，数据有效，数据准备; 9）一个或多个电气部件的功率和/或温度; 10）来自可执行指令的信息，例如软件应用或操作系统; 11）在各个时间段内的多个统计，以确定是否使用不同的带宽分配将导致更好的性能。 在本发明的实施例中，系统参数的重要性可以随时间加权。

公开(公告)号：US07755968B2

公开(公告)日：2010-07-13

申请号：US11834915

申请日：2007-08-07

Applicant: Steven Woo ,  Michael Ching ,  Chad A. Bellows ,  Wayne S. Richardson ,  Kurt T. Knorpp ,  Jun Kim

Inventor： Steven Woo ,  Michael Ching ,  Chad A. Bellows ,  Wayne S. Richardson ,  Kurt T. Knorpp ,  Jun Kim

IPC: G11C8/00

CPC classification number: G11C7/106 ,  G11C7/065 ,  G11C7/1045 ,  G11C7/1051

Abstract: An integrated circuit memory device has a storage array with an adjustable number of memory banks, a row of sense amplifiers to access storage cells in the storage array; and memory access control circuitry. The memory access control circuitry provides a first number of memory banks and a first page size in the integrated circuit memory device in a first mode of operation, and provides a second number of memory banks and a second page size in the integrated circuit memory device in a second mode of operation. The memory access control circuitry includes logic circuitry to adjust the number of memory banks in the integrated circuit memory device, and to adjust the page size of the integrated circuit memory device.

Abstract translation: 集成电路存储器件具有可调节数量的存储体的存储阵列，一行读出放大器，用于存取存储阵列中的存储单元; 和存储器访问控制电路。 存储器访问控制电路在第一操作模式下在集成电路存储器件中提供第一数量的存储体和第一页面大小，并且在集成电路存储器件中提供第二数量的存储体和第二页面尺寸 第二种操作模式。 存储器访问控制电路包括用于调整集成电路存储器件中的存储体的数量的逻辑电路，并且调整集成电路存储器件的页面大小。

公开(公告)号：US20090136676A1

公开(公告)日：2009-05-28

申请号：US12192115

申请日：2008-08-14

Applicant: Michael Ching

Inventor： Michael Ching

IPC: B05D1/18 ,  A23G3/24

CPC classification number: A23G3/24 ,  A21D13/24 ,  A23G3/0093 ,  A23L19/05 ,  A23P20/10 ,  A23P20/11 ,  B05C3/09

Abstract: An apparatus for coating at least one food item is disclosed. The apparatus includes a reservoir for housing a liquid medium, a dipping assembly operatively coupled to the reservoir wherein the dipping assembly includes a holding mechanism for holding the at least one food item, and mechanical means operatively coupled to the holding mechanism for moving the holding mechanism into the reservoir whereby the at least one food item is immersed in the liquid medium such that the at least one food item is partially coated with the liquid medium in a predetermined fashion.

Abstract translation: 公开了一种用于涂覆至少一种食品的装置。 该装置包括用于容纳液体介质的储存器，可操作地联接到储存器的浸渍组件，其中浸渍组件包括用于保持至少一个食品的保持机构，以及可操作地联接到保持机构的机构装置，用于使保持机构 进入储存器，由此将至少一个食品浸入液体介质中，使得至少一个食品以预定的方式部分地涂覆有液体介质。

公开(公告)号：US20090119291A1

公开(公告)日：2009-05-07

申请号：US12348336

申请日：2009-01-05

Applicant: Srinivasan Balasubramanian ,  Michael Ching ,  Piyoosh Jalan ,  Satish C. Penmetsa ,  Andrew S. Tomkins

Inventor： Srinivasan Balasubramanian ,  Michael Ching ,  Piyoosh Jalan ,  Satish C. Penmetsa ,  Andrew S. Tomkins

IPC: G06F17/30

CPC classification number: G06F17/30864 ,  Y10S707/99932 ,  Y10S707/99937

Abstract: A system and method of crawling at least one website comprising at least one URL includes maintaining a lookup structure comprising all of the URLs known to be on a website; calculating a hub score for each webpage of the website to be recrawled, wherein the hub score measures how likely the to be recrawled webpage includes links to fresh content published on the website; sorting all the to be recrawled pages by their hub scores; and crawling the to be recrawled pages in order from highest hub scores to lowest hub scores. The calculating comprises computing a first value equaling a percentage of a number of new relative URLs on the to be recrawled page; computing a second value equaling a percentage of a previous hub score of the to be recrawled page; and computing the hub score as a sum of the first and the second values.

Abstract translation: 一种爬行包括至少一个URL的至少一个网站的系统和方法包括维护包括已知在网站上的所有URL的查找结构; 计算要重新抓取的网站的每个网页的中心评分，其中中心评分测量重新获取的网页的可能性包括链接到在网站上发布的新鲜内容; 通过他们的中心分数排序所有要重新抓取的页面; 并从最高中心分数到最低中心分数的顺序爬行重新抓取的页面。 计算包括计算等于要重新获取的页面上的多个新的相对URL的百分比的第一值; 计算等于要重新抓取的页面的先前中心点的百分比的第二值; 以及将所述中心分数计算为所述第一和第二值的总和。

公开(公告)号：US20080256046A1

公开(公告)日：2008-10-16

申请号：US12143885

申请日：2008-06-23

Applicant: David L. Blackman ,  Michael Ching ,  Stephen Dill ,  Ivan Eduardo Gonzalez ,  Adam Marcus ,  Daniel Norin Meredith ,  Linda Anh Linh Nguyen

Inventor： David L. Blackman ,  Michael Ching ,  Stephen Dill ,  Ivan Eduardo Gonzalez ,  Adam Marcus ,  Daniel Norin Meredith ,  Linda Anh Linh Nguyen

IPC: G06F7/06 ,  G06F17/30

CPC classification number: G06F17/30864 ,  Y10S707/99934 ,  Y10S707/99935 ,  Y10S707/99936

Abstract: A system and method for prioritizing a fetch order of web pages. The method comprises extracting by a web crawler a set of candidate web pages to be crawled. Each web page in the set of candidate web pages is associated with a website in a computer network. A determination is made to determine if a first website score for the website is in a website score database. The first website score is associated with web pages in the set of candidate web pages if the first website score exists in the website score database. The set of candidate web pages is prioritized with respect to an associated website score for each web page in the candidate set of web pages. Content is retrieved from the set of candidate web. Hyperlinks are extracted from the content. The hyperlinks are stored in a memory unit.

Abstract translation: 用于优先处理网页的获取顺序的系统和方法。 该方法包括由网络爬行器提取要爬网的一组候选网页。 候选网页集合中的每个网页与计算机网络中的网站相关联。 确定确定网站的第一网站得分是否在网站得分数据库中。 如果网站得分数据库中存在第一个网站分数，则第一个网站得分与该候选网页集中的网页相关联。 候选网页的集合对于候选网页集合中的每个网页的相关网站评分是优先的。 从候选网络集中检索内容。 从内容中提取超链接。 超链接存储在存储单元中。

公开(公告)号：US20050237094A1

公开(公告)日：2005-10-27

申请号：US11148783

申请日：2005-06-08

Applicant: Donald Stark ,  Jun Kim ,  Kurt Knorpp ,  Michael Ching ,  Natsuki Kushiyama

Inventor： Donald Stark ,  Jun Kim ,  Kurt Knorpp ,  Michael Ching ,  Natsuki Kushiyama

IPC: G11C7/10 ,  H03B1/00 ,  H03K17/16 ,  H03K19/003

CPC classification number: H03K17/164 ,  G11C7/1051 ,  H03K19/00384

Abstract: An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current 5 river receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.

Abstract translation: 输出驱动器具有输出多路复用器和输出电流驱动器。 输出多路复用器接收数据信号并输出​​q-节点信号。 输出电流5河接收q节点信号，并根据q-节点信号驱动总线。 输出多路复用器以各种方式处理数据信号以产生q-结点信号。 输出电流驱动器响应于当前控制位以选择输出驱动电流的量。 此外，控制输出多路复用器，使得输出电流驱动器的输出阻抗保持在预定范围内。

公开(公告)号：US5959481A

公开(公告)日：1999-09-28

申请号：US801521

申请日：1997-02-18

Applicant: Kevin S. Donnelly ,  Chanh Tran ,  Michael Ching ,  Bruno Garlepp

Inventor： Kevin S. Donnelly ,  Chanh Tran ,  Michael Ching ,  Bruno Garlepp

IPC: G06F13/40 ,  H03K5/12

CPC classification number: G06F13/4072

Abstract: A bus driver circuit having slew rate control. According to one embodiment, the bus driver circuit includes the following elements: a first circuit having an input configured to receive a data signal and an output operative to output a drive signal in response to the data signal; a second circuit coupled in parallel with the first circuit and operative to receive a slew rate control signal; and a slew rate indicator circuit coupled to the second circuit. The slew rate indicator circuit determines the state of the slew rate control signal in response to operating conditions that cause variations in the slew rate of the drive signal such that when the slew rate control signal is asserted, the second circuit is enabled to affect the slew rate of the drive signal. For one embodiment, the slew rate indicator includes a pulse generator circuit and a clocked comparator circuit. The pulse generator circuit is operative to receive a clock signal and generate a pulse in response to a first transition of the clock signal. The clocked comparator is coupled to the pulse generator circuit and operative to receive the pulse. The clocked comparator determines the state of the slew rate control signal by sampling for the pulse in response to a second transition of the clock signal.

Abstract translation: 具有转换速率控制的总线驱动器电路。 根据一个实施例，总线驱动器电路包括以下元件：第一电路，其具有被配置为接收数据信号的输入和用于响应于数据信号输出驱动信号的输出; 第二电路，与第一电路并联并且可操作以接收压摆率控制信号; 以及耦合到第二电路的转换速率指示器电路。 压摆率指示电路响应于导致驱动信号的转换速率的变化的操作条件来确定转换速率控制信号的状态，使得当转换速率控制信号被确认时，第二电路能够影响转换 驱动信号的速率。 对于一个实施例，转换速率指示器包括脉冲发生器电路和时钟比较器电路。 脉冲发生器电路用于接收时钟信号并且响应于时钟信号的第一转换而产生脉冲。 时钟比较器耦合到脉冲发生器电路并且可操作以接收脉冲。 时钟比较器响应于时钟信号的第二次转换来确定脉冲采样的转换速率控制信号的状态。

公开(公告)号：US20160188659A1

公开(公告)日：2016-06-30

申请号：US14588290

申请日：2014-12-31

Applicant: Yuanjie Liu ,  Xiaoyuan Wu ,  Michael Ching ,  Song Feng ,  Joseph Anthony Beynon ,  David Goldberg

Inventor： Yuanjie Liu ,  Xiaoyuan Wu ,  Michael Ching ,  Song Feng ,  Joseph Anthony Beynon ,  David Goldberg

IPC: G06F17/30

CPC classification number: G06F17/30646

Abstract: Techniques for determining search results based on session based refinements are presented herein. A method is disclosed that includes receiving a query in a user session, the query comprising one or more search parameters, detecting, in the user session and after receiving the query, a user event associated with a property of an item, updating a record in a table that associates the query with the property, the table comprising a plurality of records that associate the query with respective item properties, the record comprising the query, the property, and a score, and ranking search results for a subsequent query based on the associated properties indicated in the plurality of records, the subsequent query including the one or more search parameters.

Abstract translation: 本文介绍了基于会话优化来确定搜索结果的技术。 公开了一种方法，其包括在用户会话中接收查询，所述查询包括一个或多个搜索参数，在用户会话中检测并且在接收到查询之后，检测与项目的属性相关联的用户事件， 将查询与属性相关联的表，该表包括将查询与相应项目属性相关联的多个记录，包括查询，属性和分数的记录，以及基于以下内容对后续查询进行排序的搜索结果 在多个记录中指示的相关属性，后续查询包括一个或多个搜索参数。

公开(公告)号：US09324112B2

公开(公告)日：2016-04-26

申请号：US12942577

申请日：2010-11-09

Applicant: Peter Richard Bailey ,  Chad Carson ,  Scott Joseph Counts ,  Nikhil Bharat Dandekar ,  Ho John Lee ,  Shubha Umesh Nabar ,  Aditya Pal ,  Michael Ching ,  Paul Alexander Dow ,  Shuang Guo ,  Hyun-Ju Seo

Inventor： Peter Richard Bailey ,  Chad Carson ,  Scott Joseph Counts ,  Nikhil Bharat Dandekar ,  Ho John Lee ,  Shubha Umesh Nabar ,  Aditya Pal ,  Michael Ching ,  Paul Alexander Dow ,  Shuang Guo ,  Hyun-Ju Seo

IPC: G06F17/30 ,  G06Q50/00

CPC classification number: G06Q50/01 ,  G06F17/30867

Abstract: The author ranking technique described herein is a technique to rank authors in social media systems along various dimensions, using a variety of statistical methods for utilizing those dimensions. More particularly, the technique ranks authors in social media systems through a combination of statistical techniques that leverage usage metrics, and social and topical graph characteristics. In various exemplary embodiments, the technique can rank author authority by the following: 1) temporal analysis of link sharing in which authority is computed based on a user's propensity to provide early links to web pages that subsequently become popular; 2) topical authority based on the author's links and content updates in specific topic areas; and 3) popularity and influence based on nodal properties of authors.

Abstract translation: 本文描述的作者排名技术是使用各种统计方法来利用这些维度来对各社会媒体系统中的作者进行各种维度的技术。 更具体地说，该技术通过结合利用使用度量的统计技术以及社会和局部图形特征来对社交媒体系统中的作者进行排名。 在各种示例性实施例中，该技术可以通过以下方式对作者权限进行排名：1）基于用户提供对随后变得流行的网页的早期链接的倾向来计算权限的链路共享的时间分析; 2）基于作者在特定主题领域的链接和内容更新的专题权威; 和3）基于作者的节点属性的人气和影响。