公开(公告)号：US20050237094A1

公开(公告)日：2005-10-27

申请号：US11148783

申请日：2005-06-08

申请人： Donald Stark ,  Jun Kim ,  Kurt Knorpp ,  Michael Ching ,  Natsuki Kushiyama

发明人： Donald Stark ,  Jun Kim ,  Kurt Knorpp ,  Michael Ching ,  Natsuki Kushiyama

IPC分类号： G11C7/10 ,  H03B1/00 ,  H03K17/16 ,  H03K19/003

CPC分类号： H03K17/164 ,  G11C7/1051 ,  H03K19/00384

摘要： An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current 5 river receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.

摘要翻译： 输出驱动器具有输出多路复用器和输出电流驱动器。 输出多路复用器接收数据信号并输出​​q-节点信号。 输出电流5河接收q节点信号，并根据q-节点信号驱动总线。 输出多路复用器以各种方式处理数据信号以产生q-结点信号。 输出电流驱动器响应于当前控制位以选择输出驱动电流的量。 此外，控制输出多路复用器，使得输出电流驱动器的输出阻抗保持在预定范围内。

公开(公告)号：US20060067146A1

公开(公告)日：2006-03-30

申请号：US10954941

申请日：2004-09-30

申请人： Steven Woo ,  Michael Ching ,  Chad Bellows ,  Wayne Richardson ,  Kurt Knorpp ,  Jun Kim

发明人： Steven Woo ,  Michael Ching ,  Chad Bellows ,  Wayne Richardson ,  Kurt Knorpp ,  Jun Kim

IPC分类号： G11C7/02

CPC分类号： G11C7/106 ,  G11C7/065 ,  G11C7/1045 ,  G11C7/1051

摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in dynamic memory bank count and page size mode. The integrated circuit memory device includes a first and second row of storage cells coupled to a row of sense amplifiers including a first and second plurality of sense amplifiers. During the first mode of operation, a first plurality of data is transferred from the first plurality of storage cells to the row of sense amplifiers. During the second mode of operation, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers. The second and third plurality of data is accessible simultaneously from the memory device interface during the second mode of operation. In an embodiment, the second plurality of data is transferred from the first half of the first row and the third plurality of data is transferred from the second half of the second row.

摘要翻译： 存储器系统包括主设备，诸如图形控制器或处理器，以及可以动态存储器库计数和页大小模式操作的集成电路存储器件。 集成电路存储器件包括耦合到包括第一和第二多个读出放大器的读出放大器行的第一和第二行存储单元。 在第一操作模式期间，第一多个数据从第一多个存储单元传送到读出放大器行。 在第二操作模式期间，第二多个数据从第一行存储单元转移到第一多个读出放大器，并且第三多个数据从第二行存储单元传送到第二多个读出放大器 。 在第二操作模式期间，第二和第三多个数据可以从存储器设备接口同时访问。 在一个实施例中，第二多个数据从第一行的前半部分传送，第三个数据从第二行的后半部分传送。

公开(公告)号：US20070268765A1

公开(公告)日：2007-11-22

申请号：US11834915

申请日：2007-08-07

申请人： Steven Woo ,  Michael Ching ,  Chad Bellows ,  Wayne Richardson ,  Kurt Knorpp ,  Jun Kim

发明人： Steven Woo ,  Michael Ching ,  Chad Bellows ,  Wayne Richardson ,  Kurt Knorpp ,  Jun Kim

IPC分类号： G11C7/02

CPC分类号： G11C7/106 ,  G11C7/065 ,  G11C7/1045 ,  G11C7/1051

摘要： An integrated circuit memory device has a storage array with an adjustable number of memory banks, a row of sense amplifiers to access storage cells in the storage array; and memory access control circuitry. The memory access control circuitry provides a first number of memory banks and a first page size in the integrated circuit memory device in a first mode of operation, and provides a second number of memory banks and a second page size in the integrated circuit memory device in a second mode of operation. The memory access control circuitry includes logic circuitry to adjust the number of memory banks in the integrated circuit memory device, and to adjust the page size of the integrated circuit memory device.

摘要翻译： 集成电路存储器件具有可调节数量的存储体的存储阵列，一行读出放大器，用于存取存储阵列中的存储单元; 和存储器访问控制电路。 存储器访问控制电路在第一操作模式下在集成电路存储器件中提供第一数量的存储体和第一页面大小，并且在集成电路存储器件中提供第二数量的存储体和第二页面尺寸 第二种操作模式。 存储器访问控制电路包括用于调整集成电路存储器件中的存储体的数量的逻辑电路，并且调整集成电路存储器件的页面大小。

公开(公告)号：US07755968B2

公开(公告)日：2010-07-13

申请号：US11834915

申请日：2007-08-07

申请人： Steven Woo ,  Michael Ching ,  Chad A. Bellows ,  Wayne S. Richardson ,  Kurt T. Knorpp ,  Jun Kim

发明人： Steven Woo ,  Michael Ching ,  Chad A. Bellows ,  Wayne S. Richardson ,  Kurt T. Knorpp ,  Jun Kim

IPC分类号： G11C8/00

CPC分类号： G11C7/106 ,  G11C7/065 ,  G11C7/1045 ,  G11C7/1051

摘要： An integrated circuit memory device has a storage array with an adjustable number of memory banks, a row of sense amplifiers to access storage cells in the storage array; and memory access control circuitry. The memory access control circuitry provides a first number of memory banks and a first page size in the integrated circuit memory device in a first mode of operation, and provides a second number of memory banks and a second page size in the integrated circuit memory device in a second mode of operation. The memory access control circuitry includes logic circuitry to adjust the number of memory banks in the integrated circuit memory device, and to adjust the page size of the integrated circuit memory device.

摘要翻译： 集成电路存储器件具有可调节数量的存储体的存储阵列，一行读出放大器，用于存取存储阵列中的存储单元; 和存储器访问控制电路。 存储器访问控制电路在第一操作模式下在集成电路存储器件中提供第一数量的存储体和第一页面大小，并且在集成电路存储器件中提供第二数量的存储体和第二页面尺寸 第二种操作模式。 存储器访问控制电路包括用于调整集成电路存储器件中的存储体的数量的逻辑电路，并且调整集成电路存储器件的页面大小。

公开(公告)号：US07254075B2

公开(公告)日：2007-08-07

申请号：US10954941

申请日：2004-09-30

申请人： Steven Woo ,  Michael Ching ,  Chad A. Bellows ,  Wayne S. Richardson ,  Kurt T. Knorpp ,  Jun Kim

发明人： Steven Woo ,  Michael Ching ,  Chad A. Bellows ,  Wayne S. Richardson ,  Kurt T. Knorpp ,  Jun Kim

IPC分类号： G11C7/02

CPC分类号： G11C7/106 ,  G11C7/065 ,  G11C7/1045 ,  G11C7/1051

摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in dynamic memory bank count and page size mode. The integrated circuit memory device includes a first and second row of storage cells coupled to a row of sense amplifiers including a first and second plurality of sense amplifiers. During the first mode of operation, a first plurality of data is transferred from the first plurality of storage cells to the row of sense amplifiers. During the second mode of operation, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers. The second and third plurality of data is accessible simultaneously from the memory device interface during the second mode of operation. In an embodiment, the second plurality of data is transferred from the first half of the first row and the third plurality of data is transferred from the second half of the second row.

摘要翻译： 存储器系统包括主设备，诸如图形控制器或处理器，以及可以动态存储器库计数和页大小模式操作的集成电路存储器件。 集成电路存储器件包括耦合到包括第一和第二多个读出放大器的读出放大器行的第一和第二行存储单元。 在第一操作模式期间，第一多个数据从第一多个存储单元传送到读出放大器行。 在第二操作模式期间，第二多个数据从第一行存储单元传送到第一多个读出放大器，并且第三多个数据从第二行存储单元传送到第二多个读出放大器 。 在第二操作模式期间，第二和第三多个数据可以从存储器设备接口同时访问。 在一个实施例中，第二多个数据从第一行的前半部分传送，第三个数据从第二行的后半部分传送。

公开(公告)号：US20160063109A1

公开(公告)日：2016-03-03

申请号：US14472985

申请日：2014-08-29

申请人： Yuanjie Liu ,  David Goldberg ,  Michael Ching ,  Xiaoyuan Wu ,  Joseph Anthony Beynon ,  Song Feng

发明人： Yuanjie Liu ,  David Goldberg ,  Michael Ching ,  Xiaoyuan Wu ,  Joseph Anthony Beynon ,  Song Feng

IPC分类号： G06F17/30

CPC分类号： G06F16/9535

摘要： Systems and techniques for a query-breadth selected search result sorting mechanism are herein described. A search query can be received from a user. A breadth score can be generated for the search query. A sorting mechanism can be selected from a plurality of sorting mechanisms based on the breadth score. Search results can be identified for the query and the selected sorting mechanism can be applied to the search results to produce an ordered set of search results. The ordered set of search results can be presented to the user.

摘要翻译： 这里描述了用于查询宽度选择的搜索结果分类机制的系统和技术。 可以从用户接收到搜索查询。 可以为搜索查询生成广度分数。 可以基于宽度得分从多个分选机构中选择排序机制。 可以为查询识别搜索结果，并且可以将所选择的排序机制应用于搜索结果以产生有序的搜索结果集。 搜索结果的有序集可以呈现给用户。

公开(公告)号：US07966337B2

公开(公告)日：2011-06-21

申请号：US12143885

申请日：2008-06-23

申请人： David L. Blackman ,  Michael Ching ,  Stephen Dill ,  Ivan Eduardo Gonzalez ,  Adam Marcus ,  Daniel Norin Meredith ,  Linda Anh Linh Nguyen

发明人： David L. Blackman ,  Michael Ching ,  Stephen Dill ,  Ivan Eduardo Gonzalez ,  Adam Marcus ,  Daniel Norin Meredith ,  Linda Anh Linh Nguyen

IPC分类号： G06F17/30

CPC分类号： G06F17/30864 ,  Y10S707/99934 ,  Y10S707/99935 ,  Y10S707/99936

摘要： A system and method for prioritizing a fetch order of web pages. The method comprises extracting by a web crawler a set of candidate web pages to be crawled. Each web page in the set of candidate web pages is associated with a website in a computer network. A determination is made to determine if a first website score for the website is in a website score database. The first website score is associated with web pages in the set of candidate web pages if the first website score exists in the website score database. The set of candidate web pages is prioritized with respect to an associated website score for each web page in the candidate set of web pages. Content is retrieved from the set of candidate web. Hyperlinks are extracted from the content. The hyperlinks are stored in a memory unit.

摘要翻译： 用于优先处理网页的获取顺序的系统和方法。 该方法包括由网络爬行器提取要爬网的一组候选网页。 候选网页集合中的每个网页与计算机网络中的网站相关联。 确定确定网站的第一网站得分是否在网站得分数据库中。 如果网站得分数据库中存在第一个网站分数，则第一个网站得分与该候选网页集中的网页相关联。 候选网页的集合对于候选网页集合中的每个网页的相关网站评分是优先的。 从候选网络集中检索内容。 从内容中提取超链接。 超链接存储在存储单元中。

公开(公告)号：US20060022724A1

公开(公告)日：2006-02-02

申请号：US11237276

申请日：2005-09-27

申请人： Jared Zerbe ,  Michael Ching ,  Abhijit Abhyankar ,  Richard Barth ,  Andy Chan ,  Paul Davis ,  William Stonecypher

发明人： Jared Zerbe ,  Michael Ching ,  Abhijit Abhyankar ,  Richard Barth ,  Andy Chan ,  Paul Davis ,  William Stonecypher

IPC分类号： H03L7/00

CPC分类号： G06F1/12 ,  G06F13/423 ,  H03L7/085 ,  H04L7/0012 ,  H04L7/0045 ,  H04L7/0054 ,  H04L7/02 ,  H04L7/0337

摘要： A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

公开(公告)号：US08149874B2

公开(公告)日：2012-04-03

申请号：US13110217

申请日：2011-05-18

申请人： Michael Ching ,  Steven Woo

发明人： Michael Ching ,  Steven Woo

IPC分类号： H04J3/16

CPC分类号： G06F13/4072 ,  H04L5/14 ,  H04L5/143 ,  H04L5/18 ,  H04L25/0272 ,  H04L25/0294 ,  Y02D10/14 ,  Y02D10/151

摘要： Apparatus and methods allocate I/O bandwidth of an electrical component, such as an IC, by configuring an I/O interface into various types of interfaces. In an embodiment of the present invention, an I/O interface is configured into either a bi-directional contact, unidirectional contact (including either a dedicated transmit or dedicated receive contact) or a maintenance contact used in a maintenance or calibration mode of operation. The I/O interface is periodically reconfigured to optimally allocate I/O bandwidth responsive to system parameters, such as changing data workloads in the electronic components. System parameters include, but are not limited to, 1) number of transmit-receive bus turnarounds; 2) number of transmit and/or receive data packets; 3) user selectable setting 4) number of transmit and/or receive commands; 5) direct requests from one or more electronic components; 6) number of queued transactions in one or more electronic components; 7) transmit burst-length setting, 8) duration or cycle count of bus commands, and control strobes such as address/data strobe, write enable, chip select, data valid, data ready; 9) power and/or temperature of one or more electrical components; 10) information from executable instructions, such as a software application or operating system; 11) multiple statistics over respective periods of time to determine if using a different bandwidth allocation would result in better performance. The importance of a system parameter may be weighted over time in an embodiment of the present invention.

摘要翻译： 装置和方法通过将I / O接口配置成各种类型的接口来分配诸如IC的电气部件的I / O带宽。 在本发明的实施例中，I / O接口被配置为双向接触，单向接触（包括专用发射或专用接收接点）或在维护或校准操作模式中使用的维护接点。 周期性地重新配置I / O接口，以响应于系统参数（例如改变电子组件中的数据工作负载）来最佳地分配I / O带宽。 系统参数包括但不限于：1）发送接收总线周转数; 2）发送和/或接收数据包的数量; 3）用户可选设置4）发送和/或接收命令的数量; 5）一个或多个电子元件的直接请求; 6）一个或多个电子组件中的排队交易数; 7）发送突发长度设置，8）总线命令的持续时间或周期计数，以及控制选通，如地址/数据选通，写使能，片选，数据有效，数据准备; 9）一个或多个电气部件的功率和/或温度; 10）来自可执行指令的信息，例如软件应用或操作系统; 11）在各个时间段内的多个统计，以确定是否使用不同的带宽分配将导致更好的性能。 在本发明的实施例中，系统参数的重要性可以随时间加权。

公开(公告)号：US08073009B2

公开(公告)日：2011-12-06

申请号：US12177747

申请日：2008-07-22

申请人： Michael Ching ,  Steven Woo

发明人： Michael Ching ,  Steven Woo

IPC分类号： H04J3/16

CPC分类号： G06F13/4072 ,  H04L5/14 ,  H04L5/143 ,  H04L5/18 ,  H04L25/0272 ,  H04L25/0294 ,  Y02D10/14 ,  Y02D10/151

摘要： Apparatus and methods allocate I/O bandwidth of an electrical component, such as an IC, by configuring an I/O interface into various types of interfaces. In an embodiment of the present invention, an I/O interface is configured into either a bi-directional contact, unidirectional contact (including either a dedicated transmit or dedicated receive contact) or a maintenance contact used in a maintenance or calibration mode of operation. The I/O interface is periodically reconfigured to optimally allocate I/O bandwidth responsive to system parameters, such as changing data workloads in the electronic components. System parameters include, but are not limited to, 1) number of transmit-receive bus turnarounds; 2) number of transmit and/or receive data packets; 3) user selectable setting 4) number of transmit and/or receive commands; 5) direct requests from one or more electronic components; 6) number of queued transactions in one or more electronic components; 7) transmit burst-length setting, 8) duration or cycle count of bus commands, and control strobes such as address/data strobe, write enable, chip select, data valid, data ready; 9) power and/or temperature of one or more electrical components; 10) information from executable instructions, such as a software application or operating system; 11) multiple statistics over respective periods of time to determine if using a different bandwidth allocation would result in better performance. The importance of a system parameter may be weighted over time in an embodiment of the present invention.

摘要翻译： 装置和方法通过将I / O接口配置成各种类型的接口来分配诸如IC的电气部件的I / O带宽。 在本发明的实施例中，I / O接口被配置为双向接触，单向接触（包括专用发射或专用接收接点）或在维护或校准操作模式中使用的维护接点。 周期性地重新配置I / O接口，以响应于系统参数（例如改变电子组件中的数据工作负载）来最佳地分配I / O带宽。 系统参数包括但不限于：1）发送接收总线周转数; 2）发送和/或接收数据包的数量; 3）用户可选设置4）发送和/或接收命令的数量; 5）一个或多个电子元件的直接请求; 6）一个或多个电子组件中的排队交易数; 7）发送突发长度设置，8）总线命令的持续时间或周期计数，以及控制选通，如地址/数据选通，写使能，片选，数据有效，数据准备; 9）一个或多个电气部件的功率和/或温度; 10）来自可执行指令的信息，例如软件应用或操作系统; 11）在各个时间段内的多个统计，以确定是否使用不同的带宽分配将导致更好的性能。 在本发明的实施例中，系统参数的重要性可以随时间加权。