公开(公告)号：US08327033B2

公开(公告)日：2012-12-04

申请号：US12150599

申请日：2008-04-29

Applicant: Cyrille Chavet ,  Pascal Urard ,  Philippe Coussy ,  Eric Martin

Inventor： Cyrille Chavet ,  Pascal Urard ,  Philippe Coussy ,  Eric Martin

IPC: G06F3/00 ,  G06F13/00

CPC classification number: H03M13/2775 ,  H03M13/2957 ,  H04L1/0071

Abstract: A data interleaving device is provided that includes an input, an output, and a data interleaver coupled to the input and the output. The input receives data originating from a plurality of processing blocks. The output transfers interleaved data to the plurality of processing blocks. The data interleaver includes a controller, at least one interconnection module, and a plurality of memories. The controller prepares a data-to-memory assignment data structure. The at least one interconnection module switches data in parallel according to the data-to-memory assignment data structure and acts identically on all data switched simultaneously in parallel. The plurality of memories store the switched data. The data interleaver interleaves data received from the input and provides the interleaved data at the output.

Abstract translation: 提供了一种包括耦合到输入和输出的输入，输出和数据交织器的数据交织设备。 输入接收来自多个处理块的数据。 输出将交错数据传送到多个处理块。 数据交织器包括控制器，至少一个互连模块和多个存储器。 控制器准备数据到内存分配数据结构。 至少一个互连模块根据数据到存储器分配数据结构并行地切换数据，并且对并行地同时切换的所有数据执行相同的操作。 多个存储器存储切换的数据。 数据交织器交织从输入接收的数据，并在输出端提供交错数据。

公开(公告)号：US08046658B2

公开(公告)日：2011-10-25

申请号：US11834198

申请日：2007-08-06

Applicant: Vincent Heinrich ,  Pascal Urard

Inventor： Vincent Heinrich ,  Pascal Urard

IPC: H03M13/00

CPC classification number: H03M13/1165 ,  H03M13/1105 ,  H03M13/6505 ,  H03M13/6508 ,  H03M13/6566

Abstract: A method is for decoding a succession of blocks of data encoded with an LDPC code. The method includes storing the blocks temporarily and successively in an input memory before decoding the blocks successively in an iterative manner, the input memory having a memory size for storage of at least two blocks, and defining a current indication representative of a threshold number of iterations for decoding a current block. The method includes decoding the current block until a decoding criterion is satisfied or so long as a number of iterations performed for decoding the current block has not reached the current indication while at least one of a first subsequent block and a part of a second subsequent block are stored in the input memory, and updating the current indication for decoding the first subsequent block as a function of the number of iterations performed for decoding the current block.

Abstract translation: 一种用于解码用LDPC码编码的数据块序列的方法。 该方法包括：以迭代方式连续解码块之前临时并连续地存储块，输入存储器具有用于存储至少两个块的存储器大小，并且定义表示阈值迭代次数的当前指示 用于解码当前块。 该方法包括解码当前块直到满足解码标准，或者只要对当前块解码执行的迭代次数尚未达到当前指示，而第一后续块和第二后续块的一部分中的至少一个 被存储在输入存储器中，并且根据为解码当前块执行的迭代次数来更新当前用于解码第一后续块的指示。

公开(公告)号：US20110099448A1

公开(公告)日：2011-04-28

申请号：US12605078

申请日：2009-10-23

Applicant: TINOOSH MOHSENIN ,  Bevan Baas ,  Pascal Urard

Inventor： TINOOSH MOHSENIN ,  Bevan Baas ,  Pascal Urard

IPC: H03M13/05 ,  G06F11/10

CPC classification number: H03M13/1137 ,  H03M13/1122

Abstract: A method of decoding a low density parity check (LDPC) encoded block, with the LDPC code being defined by a parity check matrix including rows, includes processing the rows of the parity check matrix. The processing includes updating data in the rows using a split-row decoding algorithm. The updating includes partitioning each row into a plurality of partitions, and determining for each partition a first local minimum of the data of the partition. The method also includes comparing for each partition the first local minimum with a threshold, and updating at least some of the data of all partitions of the row using the local minimums or the threshold depending on the results of the comparing.

Abstract translation: 解码低密度奇偶校验（LDPC）编码块的方法，其中LDPC码由包括行的奇偶校验矩阵定义，包括处理奇偶校验矩阵的行。 该处理包括使用分行解码算法更新行中的数据。 所述更新包括将每行划分成多个分区，并且为每个分区确定该分区的数据的第一局部最小值。 该方法还包括将第一局部最小值与阈值进行比较，并根据比较结果，使用局部最小值或阈值来更新行的所有分区的至少一些数据。

公开(公告)号：US20100293212A1

公开(公告)日：2010-11-18

申请号：US12777958

申请日：2010-05-11

Applicant: Laurent PAUMIER ,  Pascal URARD

Inventor： Laurent PAUMIER ,  Pascal URARD

IPC: G06F5/01

CPC classification number: G11C19/287

Abstract: A barrel shifter receiving N symbols, arranged n2 distinct groups of n1 symbols, applying a circular shift to the N symbols. The barrel shifter comprises n2 first barrel shifters, each applying a first circular shift to one of the groups of n1 symbols; a rearrangement module receiving the N symbols provided by the first barrel shifters and providing N symbols arranged, in a determined manner, in n1 distinct groups of n2 symbols; n1 second barrel shifters, each applying a second circular shift to one of the distinct groups of n2 symbols; a control module providing, to each first barrel shifter, an identical signal bs_ctrl1 representing the first shift, and providing, to each second barrel shifter, an identical signal bs_ctrl2 representing the second shift; and a switching module switching at least two of the symbols of the N symbols.

Abstract translation: 一个桶形移位器接收N个符号，排列n2个不同的n1个符号组，对N个符号进行循环移位。 桶形移位器包括n2个第一桶形移位器，每个第一桶形移位器向n1个符号组中的一个施加第一循环移位; 接收由第一桶形移位器提供的N个符号并提供以确定的方式排列在n1个不同n2个符号组中的N个符号的重排模块; n1个第二桶移位器，每个移位器向n2个符号的不同组中的一个施加第二循环移位; 控制模块向每个第一桶形移位器提供表示第一移位的相同信号bs_ctrl1，并向每个第二桶形移位器提供表示第二移位的相同信号bs_ctrl2; 以及切换模块切换N个符号的至少两个符号。

公开(公告)号：US07725810B2

公开(公告)日：2010-05-25

申请号：US11534476

申请日：2006-09-22

Applicant: Laurent Paumier ,  Pascal Urard ,  Martial Comminges

Inventor： Laurent Paumier ,  Pascal Urard ,  Martial Comminges

IPC: G06F11/00

CPC classification number: H03M13/6505 ,  H03M13/1105 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/1165 ,  H03M13/6566

Abstract: A system implemented for example in the form of an SoC comprises a first demodulator for generating a first data stream to be decoded, and a second demodulator for generating a second data stream to be decoded, and a block decoder. The block decoder comprises an input memory for storing blocks of data from the first data stream and blocks of data from the second data stream, and a block decoding unit for processing, from the input memory, the blocks of data from the first and second data streams.

Abstract translation: 以例如SoC形式实现的系统包括用于产生要解码的第一数据流的第一解调器和用于产生待解码的第二数据流的第二解调器和块解码器。 块解码器包括用于存储来自第一数据流的数据块和来自第二数据流的数据块的输入存储器，以及块解码单元，用于从输入存储器处理来自第一和第二数据的数据块 流。

公开(公告)号：US20070283209A1

公开(公告)日：2007-12-06

申请号：US11737442

申请日：2007-04-19

Applicant: Laurent Paumier ,  Pascal Urard

Inventor： Laurent Paumier ,  Pascal Urard

IPC: H03M13/05

CPC classification number: H03M13/1165 ,  H03M13/1105 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/2792

Abstract: An input memory of an LDPC decoder is loaded with data corresponding to an LDPC frame to be decoded and including N LLRs, of which K are information LLRs and N-K are parity LLRs. At least one stream is formed of binary words of a first type, each corresponding to multiple information LLRS, with the aid of a serial/parallel conversion module, and at least one stream is formed of binary words of a second type, each corresponding to multiple parity LLRs, with the aid of a row/column interlacing device comprising a two-dimensional first-in first-out ring buffer. The first memory accesses are made in page mode in order to write the binary words of the first type to a first zone of the input memory, and the second memory accesses are made in page mode in order to write the binary words of the second type to a second zone.

Abstract translation: LDPC解码器的输入存储器加载与要解码的LDPC帧相对应的数据，并且包括N个LLR，其中K是信息LLR，N-K是奇偶校验LLR。 借助于串行/并行转换模块，至少一个流由第二类型的二进制字形成，每个二进制字对应于多个信息LLRS，并且至少一个流由第二类型的二进制字形成，每一个对应于 借助于包括二维先进先出环形缓冲器的行/列交织装置的多个奇偶校验LLR。 第一存储器访问是以页模式进行的，以便将第一类型的二进制字写入输入存储器的第一区，并且第二存储器访问以页模式进行，以便写入第二类的二进制字 到第二区。

公开(公告)号：US20060251207A1

公开(公告)日：2006-11-09

申请号：US11418169

申请日：2006-05-04

Applicant: Laurent Paumier ,  Pascal Urard

Inventor： Laurent Paumier ,  Pascal Urard

IPC: G11C19/00

CPC classification number: G11C19/287

Abstract: A barrel shifter receiving N symbols, arranged n2 distinct groups of n1 symbols, applying a circular shift to the N symbols. The barrel shifter comprises n2 first barrel shifters, each applying a first circular shift to one of the groups of n1 symbols; a rearrangement module receiving the N symbols provided by the first barrel shifters and providing N symbols arranged, in a determined manner, in n1 distinct groups of n2 symbols; n1 second barrel shifters, each applying a second circular shift to one of the distinct groups of n2 symbols; a control module providing, to each first barrel shifter, an identical signal bs_ctrl1 representing the first shift, and providing, to each second barrel shifter, an identical signal bs_ctrl2 representing the second shift; and a switching module switching at least two of the symbols of the N symbols.

Abstract translation: 一个桶形移位器，接收N个符号，排列n 2个不同的n个1个符号的组，对N个符号进行循环移位。 桶形移位器包括n个2个第一桶形移位器，每个第一桶形移位器向n个1个符号组中的一个施加第一循环移位; 接收由第一桶形移位器提供的N个符号并提供以确定的方式在n个2个符号的n个不同组中排列的N个符号的重排模块; n 1个第二桶形移位器，每个第二桶形移位器向n个符号的不同组中的一个施加第二循环移位; 控制模块向每个第一桶形移位器提供表示第一移位的相同信号bs_ctrl 1，并向每个第二桶形移位器提供表示第二移位的相同信号bs_ctrl 2; 以及切换模块切换N个符号的至少两个符号。

公开(公告)号：US20050281111A1

公开(公告)日：2005-12-22

申请号：US11158718

申请日：2005-06-22

Applicant: Pascal Urard ,  Laurent Paumier

Inventor： Pascal Urard ,  Laurent Paumier

IPC: G11C7/00 ,  H03M13/11 ,  H04N7/16

CPC classification number: H03M13/6566 ,  H03M13/1137

Abstract: An LDPC decoder comprising processing units capable of receiving first messages and of providing second messages based on the first received messages; first and second single-port memories; and means for reading first words from the first and second memories, each first word containing first messages, providing first messages to the processing units based on the first read words, forming second words, each second word containing second messages provided by the processing units, and writing the second words into the first and second memories, said means being capable of reading a first (respectively second) word from the first memory and of simultaneously writing a second (respectively first) word into the second memory.

Abstract translation: 一种LDPC解码器，包括能够接收第一消息的处理单元和基于第一接收消息提供第二消息; 第一和第二单端口存储器; 以及用于从第一和第二存储器读取第一个单词的装置，每个第一个单词包含第一个消息，基于第一个读取的单词提供第一个消息给处理单元，形成第二个单词，每个第二个单词包含由处理单元提供的第二个消息， 并且将第二个字写入第一和第二存储器，所述装置能够从第一存储器读取第一（分别为第二）字，并且同时将第二（分别地）第一个字写入第二存储器。

公开(公告)号：US08635259B2

公开(公告)日：2014-01-21

申请号：US12777958

申请日：2010-05-11

Applicant: Laurent Paumier ,  Pascal Urard

Inventor： Laurent Paumier ,  Pascal Urard

IPC: G06F15/00

CPC classification number: G11C19/287

Abstract: A barrel shifter receiving N symbols, arranged n2 distinct groups of n1 symbols, applying a circular shift to the N symbols. The barrel shifter comprises n2 first barrel shifters, each applying a first circular shift to one of the groups of n1 symbols; a rearrangement module receiving the N symbols provided by the first barrel shifters and providing N symbols arranged, in a determined manner, in n1 distinct groups of n2 symbols; n1 second barrel shifters, each applying a second circular shift to one of the distinct groups of n2 symbols; a control module providing, to each first barrel shifter, an identical signal bs_ctrl1 representing the first shift, and providing, to each second barrel shifter, an identical signal bs_ctrl2 representing the second shift; and a switching module switching at least two of the symbols of the N symbols.

Abstract translation: 一个桶形移位器接收N个符号，排列n2个不同的n1个符号组，对N个符号进行循环移位。 桶形移位器包括n2个第一桶形移位器，每个第一桶形移位器向n1个符号组中的一个施加第一循环移位; 接收由第一桶形移位器提供的N个符号并提供以确定的方式排列在n1个不同n2个符号组中的N个符号的重排模块; n1个第二桶移位器，每个移位器向n2个符号的不同组中的一个施加第二循环移位; 控制模块向每个第一桶形移位器提供表示第一移位的相同信号bs_ctrl1，并向每个第二桶形移位器提供表示第二移位的相同信号bs_ctrl2; 以及切换模块切换N个符号的至少两个符号。

公开(公告)号：US20120176173A1

公开(公告)日：2012-07-12

申请号：US13174078

申请日：2011-06-30

Applicant: Chittoor PARTHASARATHY ,  Nitin Chawla ,  Kallol Chatterjee ,  Pascal Urard

Inventor： Chittoor PARTHASARATHY ,  Nitin Chawla ,  Kallol Chatterjee ,  Pascal Urard

IPC: H03K3/02 ,  H03K3/00

CPC classification number: H03K3/02 ,  H03K3/0375

Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. We present a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.

Abstract translation: 自适应缩放数字技术试图使系统接近定时故障，以最大限度地提高能量效率。 潜在故障的快速恢复通常是通过减慢系统时钟和/或提供剃须刀解决方案（指令重放）。这些技术会损害吞吐量。 我们提出一种基于动态松弛借贷提供本地原位故障恢复能力的技术。 这种技术是非侵入式的（不需要架构修改），对吞吐量影响最小。