公开(公告)号：US07853854B2

公开(公告)日：2010-12-14

申请号：US11560316

申请日：2006-11-15

Applicant: Laurent Paumier ,  Pascal Urard ,  Vincent Heinrich

Inventor： Laurent Paumier ,  Pascal Urard ,  Vincent Heinrich

IPC: H03M13/00

CPC classification number: H03M13/1105

Abstract: A method for the iterative decoding of a block of bits having a number N of bits to be decoded where N is a whole number greater than or equal to two, using an iterative decoding algorithm, comprises the generation of a current block of N intermediate decision bits by executing an iteration of the decoding algorithm, followed by the verification of a stability criterion for the current block by comparison of the current block with a given block of N reference bits. If the stability criterion is satisfied, the iterations of the iterative decoding algorithm are stopped and the current block of intermediate decision bits is delivered as a block of hard decision bits. Otherwise another iteration of the decoding algorithm is executed.

Abstract translation: 一种使用迭代解码算法对具有N个大于或等于2的整数的要解码的位数N的位块进行迭代解码的方法包括生成N个中间判决的当前块 通过执行解码算法的迭代，然后通过将当前块与给定的N个参考比特块进行比较来验证当前块的稳定性标准。 如果满足稳定性标准，则停止迭代解码算法的迭代，并将中间判定比特的当前块作为硬判决比特块传送。 否则执行解码算法的另一次迭代。

公开(公告)号：US20080052596A1

公开(公告)日：2008-02-28

申请号：US11834198

申请日：2007-08-06

Applicant: Vincent Heinrich ,  Pascal Urard

Inventor： Vincent Heinrich ,  Pascal Urard

IPC: G06F11/10

CPC classification number: H03M13/1165 ,  H03M13/1105 ,  H03M13/6505 ,  H03M13/6508 ,  H03M13/6566

Abstract: The blocks may be stored temporarily and successively in an input memory before decoding them successively in an iterative manner. The input memory has a memory size allowing the storage of more than two blocks. A current indication representative of a permitted maximum number of iterations for decoding a current block may be defined. The current indication may be initialized to a reference number of iterations increased by an additional number of iterations dependent on the additional memory size of the input memory allowing supplementary storage beyond two blocks. The current block may be decoded until a decoding criterion is satisfied or so long as the number of iterations has not reached the current indication while a first subsequent block and possibly a part of a second subsequent block are stored in the input memory. The current indication may be updated for decoding the first subsequent block as a function of the number of iterations performed for decoding the current block.

Abstract translation: 这些块可以以迭代的方式连续解码之前临时且相继地存储在输入存储器中。 输入存储器具有允许存储多于两个块的存储器大小。 可以定义表示用于解码当前块的允许的最大迭代次数的当前指示。 当前指示可以被初始化为依赖于输入存储器的附加存储器大小的附加数量的迭代增加的参考迭代次数，允许超过两个块的补充存储。 可以解码当前块，直到满足解码标准，或者只要迭代次数尚未达到当前指示，而第一后续块和可能的第二后续块的一部分存储在输入存储器中。 作为对当前块进行解码执行的迭代次数的函数的函数，可以更新当前指示以便解码第一后续块。

公开(公告)号：US20070198895A1

公开(公告)日：2007-08-23

申请号：US11560316

申请日：2006-11-15

Applicant: Laurent Paumier ,  Pascal Urard ,  Vincent Heinrich

Inventor： Laurent Paumier ,  Pascal Urard ,  Vincent Heinrich

IPC: H03M13/00

CPC classification number: H03M13/1105

Abstract: A method for the iterative decoding of a block of bits having a number N of bits to be decoded where N is a whole number greater than or equal to two, using an iterative decoding algorithm, comprises the generation of a current block of N intermediate decision bits by executing an iteration of the decoding algorithm, followed by the verification of a stability criterion for the current block by comparison of the current block with a given block of N reference bits. If the stability criterion is satisfied, the iterations of the iterative decoding algorithm are stopped and the current block of intermediate decision bits is delivered as a block of hard decision bits. Otherwise another iteration of the decoding algorithm is executed.

Abstract translation: 一种使用迭代解码算法对具有N个大于或等于2的整数的要解码的位数N的位块进行迭代解码的方法包括生成N个中间判决的当前块 通过执行解码算法的迭代，然后通过将当前块与给定的N个参考比特块进行比较来验证当前块的稳定性标准。 如果满足稳定性标准，则停止迭代解码算法的迭代，并将中间判定比特的当前块作为硬判决比特块传送。 否则执行解码算法的另一次迭代。

公开(公告)号：US08046658B2

公开(公告)日：2011-10-25

申请号：US11834198

申请日：2007-08-06

Applicant: Vincent Heinrich ,  Pascal Urard

Inventor： Vincent Heinrich ,  Pascal Urard

IPC: H03M13/00

CPC classification number: H03M13/1165 ,  H03M13/1105 ,  H03M13/6505 ,  H03M13/6508 ,  H03M13/6566

Abstract: A method is for decoding a succession of blocks of data encoded with an LDPC code. The method includes storing the blocks temporarily and successively in an input memory before decoding the blocks successively in an iterative manner, the input memory having a memory size for storage of at least two blocks, and defining a current indication representative of a threshold number of iterations for decoding a current block. The method includes decoding the current block until a decoding criterion is satisfied or so long as a number of iterations performed for decoding the current block has not reached the current indication while at least one of a first subsequent block and a part of a second subsequent block are stored in the input memory, and updating the current indication for decoding the first subsequent block as a function of the number of iterations performed for decoding the current block.

Abstract translation: 一种用于解码用LDPC码编码的数据块序列的方法。 该方法包括：以迭代方式连续解码块之前临时并连续地存储块，输入存储器具有用于存储至少两个块的存储器大小，并且定义表示阈值迭代次数的当前指示 用于解码当前块。 该方法包括解码当前块直到满足解码标准，或者只要对当前块解码执行的迭代次数尚未达到当前指示，而第一后续块和第二后续块的一部分中的至少一个 被存储在输入存储器中，并且根据为解码当前块执行的迭代次数来更新当前用于解码第一后续块的指示。

公开(公告)号：US08499228B2

公开(公告)日：2013-07-30

申请号：US12914306

申请日：2010-10-28

Applicant: Vincent Heinrich ,  Pascal Urard

Inventor： Vincent Heinrich ,  Pascal Urard

IPC: H03M13/03

CPC classification number: G11B20/1803 ,  G11B2020/10759 ,  H03M13/1111 ,  H03M13/2957 ,  H03M13/3972 ,  H03M13/4146 ,  H03M13/6343 ,  H03M13/6502

Abstract: A method is for decoding a block of N information items encoded with an error correction code and mutually correlated. The method includes carrying out a first decorrelation of the N information items of a block is carried out, and storing the block decorrelated. The method also includes a performing a processing for decoding a group of P information items of the block, and decorrelating at least part of the P decoded information items. The processing for decoding the group of P information items and the decorrelation are repeated with different successive groups of P information items of the block until the N information items of the block have been processed, until a decoding criterion is satisfied.

Abstract translation: 一种方法是解码用纠错码编码并相互相关的N个信息项的块。 该方法包括执行块的N个信息项的第一去相关，并且存储相关的块。 该方法还包括执行用于解码该块的P个信息项的处理，以及对至少部分的P个解码的信息项进行解相关。 用于解码P个信息项的组合和解相关的处理被重复，直到块的N个信息项已经被处理之前的不同的连续的P个信息项组，直到满足解码标准。

公开(公告)号：US09006851B2

公开(公告)日：2015-04-14

申请号：US13198458

申请日：2011-08-04

Applicant: Christophe Regnier ,  Olivier Hinsinger ,  Daniel Gloria ,  Pascal Urard

Inventor： Christophe Regnier ,  Olivier Hinsinger ,  Daniel Gloria ,  Pascal Urard

IPC: H01L31/0203 ,  H01L25/16 ,  H01L31/0224 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L25/16 ,  H01L21/76838 ,  H01L23/481 ,  H01L25/0652 ,  H01L31/02245 ,  H01L2223/6677 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15192 ,  Y02E10/50 ,  H01L2224/81

Abstract: A stand-alone device comprising a silicon wafer having its front surface including a first layer of a first conductivity type and a second layer of a second conductivity type forming a photovoltaic cell; first vias crossing the wafer from the rear surface of the first layer and second vias crossing the wafer from the rear surface of the second layer; metallization levels on the rear surface of the wafer, the external level of these metallization levels defining contact pads; an antenna formed in one of the metallization levels; and one or several chips assembled on said pads; the metallization levels being shaped to provide selected interconnects between the different elements of the device.

Abstract translation: 一种独立装置，包括具有其前表面的硅晶片，该硅晶片包括形成光伏电池的第一导电类型的第一层和第二导电类型的第二层; 从第一层的后表面穿过晶片的第一通孔和从第二层的后表面穿过晶片的第二过孔; 在晶片的后表面上的金属化水平，这些金属化水平的外部水平限定接触垫; 形成在金属化层之一中的天线; 以及组装在所述垫上的一个或多个芯片; 金属化水平被成形为在装置的不同元件之间提供选定的互连。

公开(公告)号：US07685502B2

公开(公告)日：2010-03-23

申请号：US11158516

申请日：2005-06-22

Applicant: Pascal Urard ,  Laurent Paumier

Inventor： Pascal Urard ,  Laurent Paumier

IPC: H03M13/00 ,  H03M13/03

CPC classification number: H03M13/1137 ,  H03M13/1105

Abstract: An LDPC decoder has a determined number of processing units operating in parallel. Storage circuitry contains first words having a juxtaposition of a first type of message. The storage circuitry also contains second words having a juxtaposition of a second type of message. A message provision unit provides each processing unit with the messages. A message write unit may write words into the storage circuitry in a way that depends on the contents of the words. The message provision unit may provide data in a way that depends on the contents of the words.

Abstract translation: LDPC解码器具有确定数量的并行操作的处理单元。 存储电路包含具有第一类型消息并置的第一个字。 存储电路还包含具有第二类型消息并置的第二字。 消息提供单元向每个处理单元提供消息。 消息写入单元可以以取决于单词的内容的方式将字写入存储电路。 消息提供单元可以以取决于单词的内容的方式提供数据。

公开(公告)号：US07139865B2

公开(公告)日：2006-11-21

申请号：US10669886

申请日：2003-09-24

Applicant: Pascal Urard

Inventor： Pascal Urard

IPC: G06F12/00

CPC classification number: G06F7/785 ,  G06F7/768

Abstract: A LIFO type data storage device of 2N depth, N being an integer, includes two random access memories each having at least 2N−1 locations for storing data. A controller controls the reading and writing of data in one or the other of the two memories, or the direct transmission of data to multiplexing means. Outputs of the two memories are also connected to the multiplexing means and the output of the device is connected to the multiplexing means via a sampler.

Abstract translation: N N为整数的LIFO型数据存储装置包括两个随机存取存储器，每个存储器具有用于存储数据的至少2个N-1个位置。 控制器控制两个存储器中的一个或另一个中的数据的读取和写入，或数据到多路复用装置的直接传输。 两个存储器的输出也连接到复用装置，并且设备的输出通过采样器连接到多路复用装置。

公开(公告)号：US20050265491A9

公开(公告)日：2005-12-01

申请号：US10841395

申请日：2004-05-07

Applicant: Pascal Urard ,  Laurent Paumier ,  Etienne Lantreibecq

Inventor： Pascal Urard ,  Laurent Paumier ,  Etienne Lantreibecq

IPC: H03M13/41 ,  H04L5/12

CPC classification number: H03M13/6505 ,  H03M13/4107

Abstract: An add-compare-select-offset device including first and second adders for generating values a and b respectively equal to the sum of first previous state and branch metrics and to the sum of second previous state and branch metrics, a calculation block for providing the greatest of values a and b on a first output and generating an adjustment value on a second output; and, a third adder for generating a current state metric equal to the sum of the outputs of the calculation block, wherein the adders perform additions without keeping the carry so that the current state metric and intermediary values a and b comprise the same number of bits as the first and second previous state metrics.

Abstract translation: 一种加法比较选择偏移装置，包括第一和第二加法器，用于产生分别等于第一先前状态和分支度量之和与第二先前状态和分支度量之和的值a和b;一个计算块，用于提供 在第一输出上最大值a和b，并在第二输出上产生调整值; 以及第三加法器，用于产生等于所述计算块的输出的和的当前状态度量，其中所述加法器在不保持进位的情况下执行相加，使得当前状态度量和中间值a和b包含相同数量的比特 作为第一和第二个状态指标。

公开(公告)号：US20050050428A1

公开(公告)日：2005-03-03

申请号：US10880334

申请日：2004-06-29

Applicant: Pascal Urard ,  Laurent Paumier ,  Etiene Lantreibecq

Inventor： Pascal Urard ,  Laurent Paumier ,  Etiene Lantreibecq

IPC: H03M13/27 ,  G06F12/00 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  G06F13/28 ,  H03M13/00

CPC classification number: H03M13/6502 ,  H03M13/27 ,  H03M13/2785 ,  H03M13/6566

Abstract: An interleaver includes two random access memories for storing data and an addressing device (100) linked to respective address inputs of the two memories. The addressing device is designed to transmit, at each instant of a clock, a cue for read access to one of the two memories and a cue for write access to the other of the two memories, so that, at each instant, a data item is written to or read from each memory.

Abstract translation: 交织器包括用于存储数据的两个随机存取存储器和连接到两个存储器的相应地址输入的寻址装置（100）。 寻址装置被设计成在时钟的每个时刻发送用于对两个存储器之一的读取访问的提示和用于对两个存储器中的另一个的写入访问的提示，使得在每个时刻，数据项 被写入或读取每个存储器。