公开(公告)号：US07685502B2

公开(公告)日：2010-03-23

申请号：US11158516

申请日：2005-06-22

Applicant: Pascal Urard ,  Laurent Paumier

Inventor： Pascal Urard ,  Laurent Paumier

IPC: H03M13/00 ,  H03M13/03

CPC classification number: H03M13/1137 ,  H03M13/1105

Abstract: An LDPC decoder has a determined number of processing units operating in parallel. Storage circuitry contains first words having a juxtaposition of a first type of message. The storage circuitry also contains second words having a juxtaposition of a second type of message. A message provision unit provides each processing unit with the messages. A message write unit may write words into the storage circuitry in a way that depends on the contents of the words. The message provision unit may provide data in a way that depends on the contents of the words.

Abstract translation: LDPC解码器具有确定数量的并行操作的处理单元。 存储电路包含具有第一类型消息并置的第一个字。 存储电路还包含具有第二类型消息并置的第二字。 消息提供单元向每个处理单元提供消息。 消息写入单元可以以取决于单词的内容的方式将字写入存储电路。 消息提供单元可以以取决于单词的内容的方式提供数据。

公开(公告)号：US20050265491A9

公开(公告)日：2005-12-01

申请号：US10841395

申请日：2004-05-07

Applicant: Pascal Urard ,  Laurent Paumier ,  Etienne Lantreibecq

Inventor： Pascal Urard ,  Laurent Paumier ,  Etienne Lantreibecq

IPC: H03M13/41 ,  H04L5/12

CPC classification number: H03M13/6505 ,  H03M13/4107

Abstract: An add-compare-select-offset device including first and second adders for generating values a and b respectively equal to the sum of first previous state and branch metrics and to the sum of second previous state and branch metrics, a calculation block for providing the greatest of values a and b on a first output and generating an adjustment value on a second output; and, a third adder for generating a current state metric equal to the sum of the outputs of the calculation block, wherein the adders perform additions without keeping the carry so that the current state metric and intermediary values a and b comprise the same number of bits as the first and second previous state metrics.

Abstract translation: 一种加法比较选择偏移装置，包括第一和第二加法器，用于产生分别等于第一先前状态和分支度量之和与第二先前状态和分支度量之和的值a和b;一个计算块，用于提供 在第一输出上最大值a和b，并在第二输出上产生调整值; 以及第三加法器，用于产生等于所述计算块的输出的和的当前状态度量，其中所述加法器在不保持进位的情况下执行相加，使得当前状态度量和中间值a和b包含相同数量的比特 作为第一和第二个状态指标。

公开(公告)号：US20050050428A1

公开(公告)日：2005-03-03

申请号：US10880334

申请日：2004-06-29

Applicant: Pascal Urard ,  Laurent Paumier ,  Etiene Lantreibecq

Inventor： Pascal Urard ,  Laurent Paumier ,  Etiene Lantreibecq

IPC: H03M13/27 ,  G06F12/00 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  G06F13/28 ,  H03M13/00

CPC classification number: H03M13/6502 ,  H03M13/27 ,  H03M13/2785 ,  H03M13/6566

Abstract: An interleaver includes two random access memories for storing data and an addressing device (100) linked to respective address inputs of the two memories. The addressing device is designed to transmit, at each instant of a clock, a cue for read access to one of the two memories and a cue for write access to the other of the two memories, so that, at each instant, a data item is written to or read from each memory.

Abstract translation: 交织器包括用于存储数据的两个随机存取存储器和连接到两个存储器的相应地址输入的寻址装置（100）。 寻址装置被设计成在时钟的每个时刻发送用于对两个存储器之一的读取访问的提示和用于对两个存储器中的另一个的写入访问的提示，使得在每个时刻，数据项 被写入或读取每个存储器。

公开(公告)号：US07925119B2

公开(公告)日：2011-04-12

申请号：US12467886

申请日：2009-05-18

Applicant: Pascal Urard ,  Laurent Paumier ,  Yan Meroth

Inventor： Pascal Urard ,  Laurent Paumier ,  Yan Meroth

IPC: G06K9/32

CPC classification number: G06T1/60 ,  G09G5/391

Abstract: An image adapter transforms an input image into an output image by successively processing tiles and by changing numbers of columns and of rows of image points. The image adapter includes queue memories connected in series so as to receive values associated with the points of a tile of the input image. A module for calculating a weighted average possesses inputs connected respectively to an output of one of the memories. The module produces values sampled in a direction parallel to the columns and corresponding to the values associated with points of the input image. A sampling rate converter, connected to the output of the module, produces values associated with the points of the output image according to a sampling rate determined for a direction parallel to the rows.

Abstract translation: 图像适配器通过连续地处理图块并且通过改变图像点的列和行的数量将输入图像转换成输出图像。 图像适配器包括串联连接的队列存储器，以便接收与输入图像的图块的点相关联的值。 用于计算加权平均的模块具有分别连接到其中一个存储器的输出的输入。 该模块产生在平行于列的方向上采样的值，并对应于与输入图像的点相关联的值。 连接到模块的输出的采样率转换器根据与行平行的方向确定的采样率产生与输出图像的点相关联的值。

公开(公告)号：US08635259B2

公开(公告)日：2014-01-21

申请号：US12777958

申请日：2010-05-11

Applicant: Laurent Paumier ,  Pascal Urard

Inventor： Laurent Paumier ,  Pascal Urard

IPC: G06F15/00

CPC classification number: G11C19/287

Abstract: A barrel shifter receiving N symbols, arranged n2 distinct groups of n1 symbols, applying a circular shift to the N symbols. The barrel shifter comprises n2 first barrel shifters, each applying a first circular shift to one of the groups of n1 symbols; a rearrangement module receiving the N symbols provided by the first barrel shifters and providing N symbols arranged, in a determined manner, in n1 distinct groups of n2 symbols; n1 second barrel shifters, each applying a second circular shift to one of the distinct groups of n2 symbols; a control module providing, to each first barrel shifter, an identical signal bs_ctrl1 representing the first shift, and providing, to each second barrel shifter, an identical signal bs_ctrl2 representing the second shift; and a switching module switching at least two of the symbols of the N symbols.

Abstract translation: 一个桶形移位器接收N个符号，排列n2个不同的n1个符号组，对N个符号进行循环移位。 桶形移位器包括n2个第一桶形移位器，每个第一桶形移位器向n1个符号组中的一个施加第一循环移位; 接收由第一桶形移位器提供的N个符号并提供以确定的方式排列在n1个不同n2个符号组中的N个符号的重排模块; n1个第二桶移位器，每个移位器向n2个符号的不同组中的一个施加第二循环移位; 控制模块向每个第一桶形移位器提供表示第一移位的相同信号bs_ctrl1，并向每个第二桶形移位器提供表示第二移位的相同信号bs_ctrl2; 以及切换模块切换N个符号的至少两个符号。

公开(公告)号：US07853854B2

公开(公告)日：2010-12-14

申请号：US11560316

申请日：2006-11-15

Applicant: Laurent Paumier ,  Pascal Urard ,  Vincent Heinrich

Inventor： Laurent Paumier ,  Pascal Urard ,  Vincent Heinrich

IPC: H03M13/00

CPC classification number: H03M13/1105

Abstract: A method for the iterative decoding of a block of bits having a number N of bits to be decoded where N is a whole number greater than or equal to two, using an iterative decoding algorithm, comprises the generation of a current block of N intermediate decision bits by executing an iteration of the decoding algorithm, followed by the verification of a stability criterion for the current block by comparison of the current block with a given block of N reference bits. If the stability criterion is satisfied, the iterations of the iterative decoding algorithm are stopped and the current block of intermediate decision bits is delivered as a block of hard decision bits. Otherwise another iteration of the decoding algorithm is executed.

Abstract translation: 一种使用迭代解码算法对具有N个大于或等于2的整数的要解码的位数N的位块进行迭代解码的方法包括生成N个中间判决的当前块 通过执行解码算法的迭代，然后通过将当前块与给定的N个参考比特块进行比较来验证当前块的稳定性标准。 如果满足稳定性标准，则停止迭代解码算法的迭代，并将中间判定比特的当前块作为硬判决比特块传送。 否则执行解码算法的另一次迭代。

公开(公告)号：US20070198896A1

公开(公告)日：2007-08-23

申请号：US11563595

申请日：2006-11-27

Applicant: Laurent Paumier ,  Pascal Urard

Inventor： Laurent Paumier ,  Pascal Urard

IPC: H03M13/00

CPC classification number: H03M13/1105 ,  H03M13/152 ,  H03M13/1555 ,  H03M13/1595 ,  H03M13/2906

Abstract: A concatenated channel decoding method wherein the bits of a set of N1 bits decoded using a first iterative block decoding algorithm and intended to be decoded using a second block decoding algorithm, are sent in parallel in at least one subset of P bits to a buffer for temporary storage. The decoding method comprises receiving in parallel at least one subset of Q bits belonging to the set of N1 bits sent to the buffer, detecting errors with the help of the second decoding algorithm, based on the bits decoded using the first decoding algorithm, and correcting the bits stored in the buffer as a function of possible errors detected. Detecting errors and/or the correcting the stored bits comprise a parallel processing of the bits of each subset of Q bits received.

Abstract translation: 一种级联信道解码方法，其中使用第一迭代块解码算法解码并且想要使用第二块解码算法进行解码的一组N1比特的比特在P比特的至少一个子集中并行发送到缓冲器， 临时存储。 解码方法包括：并行地接收属于发送到缓冲器的N1比特组的Q比特的至少一个子集，借助于第二解码算法检测错误，基于使用第一解码算法解码的比特，以及校正 存储在缓冲器中的位可以作为检测到的可能错误的函数。 检测错误和/或校正所存储的比特包括接收的Q位的每个子集的比特的并行处理。

公开(公告)号：US20070198895A1

公开(公告)日：2007-08-23

申请号：US11560316

申请日：2006-11-15

Applicant: Laurent Paumier ,  Pascal Urard ,  Vincent Heinrich

Inventor： Laurent Paumier ,  Pascal Urard ,  Vincent Heinrich

IPC: H03M13/00

CPC classification number: H03M13/1105

Abstract: A method for the iterative decoding of a block of bits having a number N of bits to be decoded where N is a whole number greater than or equal to two, using an iterative decoding algorithm, comprises the generation of a current block of N intermediate decision bits by executing an iteration of the decoding algorithm, followed by the verification of a stability criterion for the current block by comparison of the current block with a given block of N reference bits. If the stability criterion is satisfied, the iterations of the iterative decoding algorithm are stopped and the current block of intermediate decision bits is delivered as a block of hard decision bits. Otherwise another iteration of the decoding algorithm is executed.

Abstract translation: 一种使用迭代解码算法对具有N个大于或等于2的整数的要解码的位数N的位块进行迭代解码的方法包括生成N个中间判决的当前块 通过执行解码算法的迭代，然后通过将当前块与给定的N个参考比特块进行比较来验证当前块的稳定性标准。 如果满足稳定性标准，则停止迭代解码算法的迭代，并将中间判定比特的当前块作为硬判决比特块传送。 否则执行解码算法的另一次迭代。

公开(公告)号：US07725810B2

公开(公告)日：2010-05-25

申请号：US11534476

申请日：2006-09-22

Applicant: Laurent Paumier ,  Pascal Urard ,  Martial Comminges

Inventor： Laurent Paumier ,  Pascal Urard ,  Martial Comminges

IPC: G06F11/00

CPC classification number: H03M13/6505 ,  H03M13/1105 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/1165 ,  H03M13/6566

Abstract: A system implemented for example in the form of an SoC comprises a first demodulator for generating a first data stream to be decoded, and a second demodulator for generating a second data stream to be decoded, and a block decoder. The block decoder comprises an input memory for storing blocks of data from the first data stream and blocks of data from the second data stream, and a block decoding unit for processing, from the input memory, the blocks of data from the first and second data streams.

Abstract translation: 以例如SoC形式实现的系统包括用于产生要解码的第一数据流的第一解调器和用于产生待解码的第二数据流的第二解调器和块解码器。 块解码器包括用于存储来自第一数据流的数据块和来自第二数据流的数据块的输入存储器，以及块解码单元，用于从输入存储器处理来自第一和第二数据的数据块 流。

公开(公告)号：US20070283209A1

公开(公告)日：2007-12-06

申请号：US11737442

申请日：2007-04-19

Applicant: Laurent Paumier ,  Pascal Urard

Inventor： Laurent Paumier ,  Pascal Urard

IPC: H03M13/05

CPC classification number: H03M13/1165 ,  H03M13/1105 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/2792

Abstract: An input memory of an LDPC decoder is loaded with data corresponding to an LDPC frame to be decoded and including N LLRs, of which K are information LLRs and N-K are parity LLRs. At least one stream is formed of binary words of a first type, each corresponding to multiple information LLRS, with the aid of a serial/parallel conversion module, and at least one stream is formed of binary words of a second type, each corresponding to multiple parity LLRs, with the aid of a row/column interlacing device comprising a two-dimensional first-in first-out ring buffer. The first memory accesses are made in page mode in order to write the binary words of the first type to a first zone of the input memory, and the second memory accesses are made in page mode in order to write the binary words of the second type to a second zone.

Abstract translation: LDPC解码器的输入存储器加载与要解码的LDPC帧相对应的数据，并且包括N个LLR，其中K是信息LLR，N-K是奇偶校验LLR。 借助于串行/并行转换模块，至少一个流由第二类型的二进制字形成，每个二进制字对应于多个信息LLRS，并且至少一个流由第二类型的二进制字形成，每一个对应于 借助于包括二维先进先出环形缓冲器的行/列交织装置的多个奇偶校验LLR。 第一存储器访问是以页模式进行的，以便将第一类型的二进制字写入输入存储器的第一区，并且第二存储器访问以页模式进行，以便写入第二类的二进制字 到第二区。