公开(公告)号：US09006851B2

公开(公告)日：2015-04-14

申请号：US13198458

申请日：2011-08-04

Applicant: Christophe Regnier ,  Olivier Hinsinger ,  Daniel Gloria ,  Pascal Urard

Inventor： Christophe Regnier ,  Olivier Hinsinger ,  Daniel Gloria ,  Pascal Urard

IPC: H01L31/0203 ,  H01L25/16 ,  H01L31/0224 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L25/16 ,  H01L21/76838 ,  H01L23/481 ,  H01L25/0652 ,  H01L31/02245 ,  H01L2223/6677 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15192 ,  Y02E10/50 ,  H01L2224/81

Abstract: A stand-alone device comprising a silicon wafer having its front surface including a first layer of a first conductivity type and a second layer of a second conductivity type forming a photovoltaic cell; first vias crossing the wafer from the rear surface of the first layer and second vias crossing the wafer from the rear surface of the second layer; metallization levels on the rear surface of the wafer, the external level of these metallization levels defining contact pads; an antenna formed in one of the metallization levels; and one or several chips assembled on said pads; the metallization levels being shaped to provide selected interconnects between the different elements of the device.

Abstract translation: 一种独立装置，包括具有其前表面的硅晶片，该硅晶片包括形成光伏电池的第一导电类型的第一层和第二导电类型的第二层; 从第一层的后表面穿过晶片的第一通孔和从第二层的后表面穿过晶片的第二过孔; 在晶片的后表面上的金属化水平，这些金属化水平的外部水平限定接触垫; 形成在金属化层之一中的天线; 以及组装在所述垫上的一个或多个芯片; 金属化水平被成形为在装置的不同元件之间提供选定的互连。

公开(公告)号：US07685502B2

公开(公告)日：2010-03-23

申请号：US11158516

申请日：2005-06-22

Applicant: Pascal Urard ,  Laurent Paumier

Inventor： Pascal Urard ,  Laurent Paumier

IPC: H03M13/00 ,  H03M13/03

CPC classification number: H03M13/1137 ,  H03M13/1105

Abstract: An LDPC decoder has a determined number of processing units operating in parallel. Storage circuitry contains first words having a juxtaposition of a first type of message. The storage circuitry also contains second words having a juxtaposition of a second type of message. A message provision unit provides each processing unit with the messages. A message write unit may write words into the storage circuitry in a way that depends on the contents of the words. The message provision unit may provide data in a way that depends on the contents of the words.

Abstract translation: LDPC解码器具有确定数量的并行操作的处理单元。 存储电路包含具有第一类型消息并置的第一个字。 存储电路还包含具有第二类型消息并置的第二字。 消息提供单元向每个处理单元提供消息。 消息写入单元可以以取决于单词的内容的方式将字写入存储电路。 消息提供单元可以以取决于单词的内容的方式提供数据。

公开(公告)号：US07139865B2

公开(公告)日：2006-11-21

申请号：US10669886

申请日：2003-09-24

Applicant: Pascal Urard

Inventor： Pascal Urard

IPC: G06F12/00

CPC classification number: G06F7/785 ,  G06F7/768

Abstract: A LIFO type data storage device of 2N depth, N being an integer, includes two random access memories each having at least 2N−1 locations for storing data. A controller controls the reading and writing of data in one or the other of the two memories, or the direct transmission of data to multiplexing means. Outputs of the two memories are also connected to the multiplexing means and the output of the device is connected to the multiplexing means via a sampler.

Abstract translation: N N为整数的LIFO型数据存储装置包括两个随机存取存储器，每个存储器具有用于存储数据的至少2个N-1个位置。 控制器控制两个存储器中的一个或另一个中的数据的读取和写入，或数据到多路复用装置的直接传输。 两个存储器的输出也连接到复用装置，并且设备的输出通过采样器连接到多路复用装置。

公开(公告)号：US20050265491A9

公开(公告)日：2005-12-01

申请号：US10841395

申请日：2004-05-07

Applicant: Pascal Urard ,  Laurent Paumier ,  Etienne Lantreibecq

Inventor： Pascal Urard ,  Laurent Paumier ,  Etienne Lantreibecq

IPC: H03M13/41 ,  H04L5/12

CPC classification number: H03M13/6505 ,  H03M13/4107

Abstract: An add-compare-select-offset device including first and second adders for generating values a and b respectively equal to the sum of first previous state and branch metrics and to the sum of second previous state and branch metrics, a calculation block for providing the greatest of values a and b on a first output and generating an adjustment value on a second output; and, a third adder for generating a current state metric equal to the sum of the outputs of the calculation block, wherein the adders perform additions without keeping the carry so that the current state metric and intermediary values a and b comprise the same number of bits as the first and second previous state metrics.

Abstract translation: 一种加法比较选择偏移装置，包括第一和第二加法器，用于产生分别等于第一先前状态和分支度量之和与第二先前状态和分支度量之和的值a和b;一个计算块，用于提供 在第一输出上最大值a和b，并在第二输出上产生调整值; 以及第三加法器，用于产生等于所述计算块的输出的和的当前状态度量，其中所述加法器在不保持进位的情况下执行相加，使得当前状态度量和中间值a和b包含相同数量的比特 作为第一和第二个状态指标。

公开(公告)号：US20050050428A1

公开(公告)日：2005-03-03

申请号：US10880334

申请日：2004-06-29

Applicant: Pascal Urard ,  Laurent Paumier ,  Etiene Lantreibecq

Inventor： Pascal Urard ,  Laurent Paumier ,  Etiene Lantreibecq

IPC: H03M13/27 ,  G06F12/00 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  G06F13/28 ,  H03M13/00

CPC classification number: H03M13/6502 ,  H03M13/27 ,  H03M13/2785 ,  H03M13/6566

Abstract: An interleaver includes two random access memories for storing data and an addressing device (100) linked to respective address inputs of the two memories. The addressing device is designed to transmit, at each instant of a clock, a cue for read access to one of the two memories and a cue for write access to the other of the two memories, so that, at each instant, a data item is written to or read from each memory.

Abstract translation: 交织器包括用于存储数据的两个随机存取存储器和连接到两个存储器的相应地址输入的寻址装置（100）。 寻址装置被设计成在时钟的每个时刻发送用于对两个存储器之一的读取访问的提示和用于对两个存储器中的另一个的写入访问的提示，使得在每个时刻，数据项 被写入或读取每个存储器。

公开(公告)号：US08627153B2

公开(公告)日：2014-01-07

申请号：US12676802

申请日：2008-09-02

Applicant: Adrian Voicila ,  David Declercq ,  Marc Fossorier ,  François Verdier ,  Pascal Urard

Inventor： Adrian Voicila ,  David Declercq ,  Marc Fossorier ,  François Verdier ,  Pascal Urard

IPC: H03M1/18

CPC classification number: H03M13/1171 ,  H03M13/1134 ,  H03M13/114 ,  H03M13/116 ,  H03M13/118 ,  H03M13/6502

Abstract: A string of K initial symbols is encoded with a code of the parity check type. The K initial symbols belong to a Galois field of order q strictly greater than 2. The code is defined by code characteristics representable by a graph (GRH) comprising N−K first nodes (NCi), each node satisfying a parity check equation defined on the Galois field of order q, N packets of intermediate nodes (NITi) and NI second nodes (NSSi), each intermediate node being linked to a single first node and to several second nodes by way of a connection scheme. The string of K initial symbols is encoded by using the said code characteristics and a string of N encoded symbols is obtained, respectively subdivided into NI sub-symbols belonging respectively to mathematical sets whose orders are less than q, according to a subdivision scheme representative of the connection scheme (Π).

Abstract translation: 一组K个初始符号用奇偶校验类型的代码编码。 K个初始符号属于严格大于2的秩序q的Galois域。该码由包括NK第一节点（NCi）的图形（GRH）可表示的代码特征定义，每个节点满足在Galois上定义的奇偶校验方程 中间节点（NITi）和NI第二节点（NSSi）的N个分组，每个中间节点通过连接方案链接到单个第一节点和几个第二节点。 通过使用所述代码特征对K个初始符号的串进行编码，并且获得一组N个编码符号，分别被分为归属于小于q的数学集的NI子符号，根据代表 连接方案（Pi）。

公开(公告)号：US08552765B2

公开(公告)日：2013-10-08

申请号：US13174078

申请日：2011-06-30

Applicant: Chittoor Parthasarathy ,  Nitin Chawla ,  Kallol Chatterjee ,  Pascal Urard

Inventor： Chittoor Parthasarathy ,  Nitin Chawla ,  Kallol Chatterjee ,  Pascal Urard

IPC: G01R29/02

CPC classification number: H03K3/02 ,  H03K3/0375

Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. We present a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.

Abstract translation: 自适应缩放数字技术试图使系统接近定时故障，以最大限度地提高能量效率。 潜在故障的快速恢复通常是通过减慢系统时钟和/或提供剃须刀解决方案（指令重放）。这些技术会损害吞吐量。 我们提出一种基于动态松弛借贷提供本地原位故障恢复能力的技术。 这种技术是非侵入式的（不需要架构修改），对吞吐量影响最小。

公开(公告)号：US20120117391A1

公开(公告)日：2012-05-10

申请号：US13243661

申请日：2011-09-23

Applicant: David Jacquet ,  Fabrice Blisson ,  Christophe Lecocq ,  Pascal Urard ,  Pascale Robert

Inventor： David Jacquet ,  Fabrice Blisson ,  Christophe Lecocq ,  Pascal Urard ,  Pascale Robert

IPC: G06F1/26

CPC classification number: G11C5/147 ,  G06F1/263 ,  G06F1/3296 ,  Y02D10/172

Abstract: A method and system for managing the power supply of a component and of a memory cooperating with the component are disclosed. The component and the memory are powered with a first variable power supply source having a first power supply voltage level greater than a minimum operating voltage of the memory. When a voltage level of the first power supply source drops and reaches a threshold that is greater than or equal to the minimum operating voltage of the memory, the power supply of the memory is toggled to a second power supply source having a second voltage level that is greater than or equal to the minimum operating voltage of the memory.

Abstract translation: 公开了一种用于管理组件和与组件协作的存储器的电源的方法和系统。 组件和存储器由具有大于存储器的最小工作电压的第一电源电压电平的第一可变电源供电。 当第一电源的电压下降并达到大于或等于存储器的最小工作电压的阈值时，存储器的电源被切换到具有第二电压电平的第二电源电平， 大于或等于存储器的最小工作电压。

公开(公告)号：US20110113304A1

公开(公告)日：2011-05-12

申请号：US12914306

申请日：2010-10-28

Applicant: Vincent HEINRICH ,  Pascal URARD

Inventor： Vincent HEINRICH ,  Pascal URARD

IPC: H03M13/05 ,  G06F11/10

CPC classification number: G11B20/1803 ,  G11B2020/10759 ,  H03M13/1111 ,  H03M13/2957 ,  H03M13/3972 ,  H03M13/4146 ,  H03M13/6343 ,  H03M13/6502

Abstract: A method is for decoding a block of N information items encoded with an error correction code and mutually correlated. The method includes carrying out a first decorrelation of the N information items of a block is carried out, and storing the block decorrelated. The method also includes a performing a processing for decoding a group of P information items of the block, and decorrelating at least part of the P decoded information items. The processing for decoding the group of P information items and the decorrelation are repeated with different successive groups of P information items of the block until the N information items of the block have been processed, until a decoding criterion is satisfied.

Abstract translation: 一种方法是解码用纠错码编码并相互相关的N个信息项的块。 该方法包括执行块的N个信息项的第一去相关，并且存储相关的块。 该方法还包括执行用于解码该块的P个信息项的处理，以及对至少部分的P个解码的信息项进行解相关。 用于解码P个信息项的组合和解相关的处理被重复，直到块的N个信息项已经被处理之前的不同的连续的P个信息项组，直到满足解码标准。

公开(公告)号：US07925119B2

公开(公告)日：2011-04-12

申请号：US12467886

申请日：2009-05-18

Applicant: Pascal Urard ,  Laurent Paumier ,  Yan Meroth

Inventor： Pascal Urard ,  Laurent Paumier ,  Yan Meroth

IPC: G06K9/32

CPC classification number: G06T1/60 ,  G09G5/391

Abstract: An image adapter transforms an input image into an output image by successively processing tiles and by changing numbers of columns and of rows of image points. The image adapter includes queue memories connected in series so as to receive values associated with the points of a tile of the input image. A module for calculating a weighted average possesses inputs connected respectively to an output of one of the memories. The module produces values sampled in a direction parallel to the columns and corresponding to the values associated with points of the input image. A sampling rate converter, connected to the output of the module, produces values associated with the points of the output image according to a sampling rate determined for a direction parallel to the rows.

Abstract translation: 图像适配器通过连续地处理图块并且通过改变图像点的列和行的数量将输入图像转换成输出图像。 图像适配器包括串联连接的队列存储器，以便接收与输入图像的图块的点相关联的值。 用于计算加权平均的模块具有分别连接到其中一个存储器的输出的输入。 该模块产生在平行于列的方向上采样的值，并对应于与输入图像的点相关联的值。 连接到模块的输出的采样率转换器根据与行平行的方向确定的采样率产生与输出图像的点相关联的值。