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    TEST DESIGN OPTIMIZER FOR CONFIGURABLE SCAN ARCHITECTURES
    12.
    发明申请
    TEST DESIGN OPTIMIZER FOR CONFIGURABLE SCAN ARCHITECTURES 有权
    用于可配置扫描架构的测试设计优化器

    公开(公告)号：US20100017760A1

    公开(公告)日：2010-01-21

    申请号：US12248710

    申请日：2008-10-09

    Applicant: Rohit Kapur ,  Jyotirmoy Saikia ,  Rajesh Uppuluri ,  Pramod Notiyath ,  Tammy Fernandes ,  Santosh Kulkarni ,  Ashok Anbalan

    Inventor： Rohit Kapur ,  Jyotirmoy Saikia ,  Rajesh Uppuluri ,  Pramod Notiyath ,  Tammy Fernandes ,  Santosh Kulkarni ,  Ashok Anbalan

    IPC: G06F17/50

    CPC classification number: G01R31/318544 ,  G01R31/318583

    Abstract: Roughly described, a scan-based test architecture is optimized in dependence upon the circuit design under consideration. In one embodiment, a plurality of candidate test designs are developed. For each, a plurality of test vectors are generated in dependence upon the circuit design and the candidate test design, preferably using the same ATPG algorithm that will be used downstream to generate the final test vectors for the production integrated circuit device. A test protocol quality measure such as fault coverage is determined for each of the candidate test designs, and one of the candidate test designs is selected for implementation in an integrated circuit device in dependence upon a comparison of such test protocol quality measures. Preferably, only a sampling of the full set of test vectors that ATPG could generate, is used to determine the number of potential faults that would be found by each particular candidate test design.

    Abstract translation: 大致描述，基于扫描的测试架构根据所考虑的电路设计进行优化。 在一个实施例中，开发了多个候选测试设计。 对于每个，根据电路设计和候选测试设计产生多个测试向量，优选地使用将在下游用于生成用于生产集成电路器件的最终测试向量的相同ATPG算法。 确定每个候选测试设计的测试协议质量测量例如故障覆盖，并且根据这种测试协议质量度量的比较，选择一个候选测试设计用于在集成电路设备中实现。 优选地，仅使用ATPG可以产生的全套测试向量的采样来确定每个特定候选测试设计将会发现的潜在故障的数量。

    Method and apparatus for limiting power dissipation in test
    13.
    发明申请
    Method and apparatus for limiting power dissipation in test 有权
    测试中限制功耗的方法和装置

    公开(公告)号：US20080141188A1

    公开(公告)日：2008-06-12

    申请号：US11635155

    申请日：2006-12-07

    Applicant: Rohit Kapur ,  Thomas W. Williams

    Inventor： Rohit Kapur ,  Thomas W. Williams

    IPC: G06F19/00 ,  G06F17/50

    CPC classification number: G01R31/318572

    Abstract: An embodiment provides a system for testing a circuit. During operation, the system scans-in input values into a first set of flip-flops. The outputs of the first set of flip-flops are coupled with the inputs of a circuit under test, the outputs of the circuit are coupled with the inputs of a set of multiplexers, and the outputs of the set of multiplexers are coupled with the inputs of a second set of flip-flops. Next, the system configures the set of multiplexers using a segment-selection circuit, which causes the outputs of the circuit to be coupled with the inputs of the second set of flip-flops. The system then captures the circuit's output values using the second set of flip-flops. Next, the system scans-out the circuit's output values using the second set of flip-flops. Finally, the system determines whether the chip has a fault using the output values.

    Abstract translation: 实施例提供了一种用于测试电路的系统。 在操作期间，系统将输入值扫描到第一组触发器中。 第一组触发器的输出与待测电路的输入耦合，电路的输出与一组多路复用器的输入耦合，并且多路复用器组的输出与输入端耦合 的第二组触发器。 接下来，系统使用段选择电路配置多路复用器组，其使得电路的输出与第二组触发器的输入耦合。 系统然后使用第二组触发器捕获电路的输出值。 接下来，系统使用第二组触发器扫描电路的输出值。 最后，系统使用输出值确定芯片是否有故障。

    Implementing hierarchical design-for-test logic for modular circuit design
    15.
    发明授权
    Implementing hierarchical design-for-test logic for modular circuit design 有权
    实现模块化电路设计的分层设计测试逻辑

    公开(公告)号：US08065651B2

    公开(公告)日：2011-11-22

    申请号：US12362284

    申请日：2009-01-29

    Applicant: Rohit Kapur ,  Anshuman Chandra ,  Yasunari Kanzawa ,  Jyotirmoy Saikia

    Inventor： Rohit Kapur ,  Anshuman Chandra ,  Yasunari Kanzawa ,  Jyotirmoy Saikia

    IPC: G06F17/50

    CPC classification number: G01R31/318547

    Abstract: Embodiments of the present invention provide methods and apparatuses for implementing hierarchical design-for-test (DFT) logic on a circuit. The hierarchical DFT logic implements DFT circuitry that can be dedicated to a module, and which can configure DFT circuitry for multiple modules to share a sequential input signal and/or to share a sequential output signal. During operation, the DFT circuitry for a first module can propagate a bit sequence from the sequential input signal to the DFT circuitry of a second module, such that the bit sequence can include a set of control signal values for controlling the DFT circuitry, and can include compressed test vectors for testing the modules. Furthermore, the DFT circuitry for the second module can generate a sequential response signal, which combines the compressed response vectors from the second module and a sequential response signal from the DFT circuitry of the first module.

    Abstract translation: 本发明的实施例提供了用于在电路上实现分层设计测试（DFT）逻辑的方法和装置。 分层DFT逻辑实现可以专用于模块的DFT电路，并且其可以配置用于多个模块的DFT电路以共享顺序输入信号和/或共享顺序输出信号。 在操作期间，用于第一模块的DFT电路可以将比特序列从顺序输入信号传播到第二模块的DFT电路，使得比特序列可以包括用于控制DFT电路的一组控制信号值，并且可以 包括用于测试模块的压缩测试向量。 此外，用于第二模块的DFT电路可以产生顺序响应信号，其结合来自第二模块的压缩响应向量和来自第一模块的DFT电路的顺序响应信号。

    Slack-based transition-fault testing
    16.
    发明授权
    Slack-based transition-fault testing 有权
    基于松弛的过渡故障测试

    公开(公告)号：US07797601B2

    公开(公告)日：2010-09-14

    申请号：US12469820

    申请日：2009-05-21

    Applicant: Rohit Kapur ,  Tom W. Williams ,  Cyrus Hay

    Inventor： Rohit Kapur ,  Tom W. Williams ,  Cyrus Hay

    IPC: G01R31/28 ,  G01R31/30 ,  G01R31/26 ,  G11B20/20 ,  G06F9/45

    CPC classification number: G01R31/31725

    Abstract: A system that generates test patterns for detecting transition faults in an integrated circuit (IC). During operation, the system receives slack times for each net in the IC. Note that a slack time for a net is the minimum amount of delay that the given net can tolerate before violating a timing constraint. For each possible transition fault in the IC, the system uses the slack times for nets in the IC to generate a test pattern which exposes the transition fault by producing a transition that propagates along the longest path to the transition fault.

    Abstract translation: 一种生成用于检测集成电路（IC）中的过渡故障的测试模式的系统。 在操作期间，系统为IC中的每个网络收到松弛时间。 请注意，网络的松弛时间是给定网络在违反时序约束之前可以容忍的最小延迟时间。 对于IC中的每个可能的过渡故障，系统使用IC中的网络的松弛时间来产生测试模式，该测试模式通过产生沿着最长路径传播到转换故障的转变来暴露过渡故障。

    Deterministic bist architecture including MISR filter
    20.
    发明授权
    Deterministic bist architecture including MISR filter 有权
    确定性bist架构，包括MISR过滤器

    公开(公告)号：US06993694B1

    公开(公告)日：2006-01-31

    申请号：US10117747

    申请日：2002-04-05

    Applicant: Rohit Kapur ,  Thomas W. Williams ,  Tony Taylor ,  Peter Wohl ,  John A. Waicukauski

    Inventor： Rohit Kapur ,  Thomas W. Williams ,  Tony Taylor ,  Peter Wohl ,  John A. Waicukauski

    IPC: G01R31/28 ,  G01R31/08

    CPC classification number: G01R31/318547 ,  G01R31/318558

    Abstract: A filter for preventing uncertain bits output by test scan chains from being provided to a MISR is provided. The filter can include a gating structure for receiving a bit from a scan chain and control circuitry for providing a predetermined signal to the gating structure if the bit is an uncertain bit. In one embodiment, the gating structure can include a logic gate, such as an AND or an OR gate. The control circuitry can include components substantially similar to the pattern generator providing signals to the scan chain. For example, the control circuitry can include an LFSR and a PRPG shadow for loading the LFSR. In one embodiment, the control circuitry can further include a phase-shifter for receiving inputs from the LFSR and providing outputs to the gating structure.

    Abstract translation: 提供了一种用于防止测试扫描链输出的不确定位提供给MISR的滤波器。 滤波器可以包括用于从扫描链接收比特的选通结构和用于如果该比特是不确定比特，则向选通结构提供预定信号的控制电路。 在一个实施例中，门控结构可以包括逻辑门，诸如AND或OR门。 控制电路可以包括与向扫描链提供信号的图案发生器基本相似的组件。 例如，控制电路可以包括用于加载LFSR的LFSR和PRPG阴影。 在一个实施例中，控制电路还可以包括用于接收来自LFSR的输入并向门控结构提供输出的移相器。

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