PERMANENT MAGNET SYNCHRONOUS MOTOR (PMSM) AND METHOD FOR STARTING THE PMSM

    公开(公告)号:US20230387845A1

    公开(公告)日:2023-11-30

    申请号:US17828413

    申请日:2022-05-31

    发明人: Na Zhang

    IPC分类号: H02P21/34 H02P21/10

    摘要: A method of starting a permanent magnet synchronous motor (PMSM) with field oriented control (FOC) includes: opening a first control loop of the PMSM; setting a first direction for a first current component of the PMSM; aligning a rotor of the PMSM to the first direction; after aligning the rotor, setting a second direction for the first current component, where the second direction is rotated from the first direction by 90 degrees; after setting the second direction, starting the rotor while the first control loop of the PMSM remains open; after starting the rotor, increasing a rotation speed of the rotor by operating the first control loop in a first closed-loop mode; and after increasing the rotation speed of the rotor, controlling the rotation speed of the rotor by operating the first control loop in a second closed-loop mode different from the first closed-loop mode.

    CAPSULE ENDOSCOPE
    13.
    发明申请
    CAPSULE ENDOSCOPE 审中-公开
    胶囊内窥镜

    公开(公告)号:US20160109235A1

    公开(公告)日:2016-04-21

    申请号:US14978688

    申请日:2015-12-22

    摘要: An embodiment comprises and apparatus having an image capture device with an image axis and a gyroscope operable to indicate the orientation of the image axis. An embodiment of a capsule endoscopy system comprises an imaging capsule and an external unit. The imaging capsule may comprise an image capture device having an image axis and a gyroscope operable to indicate the orientation of the image axis. The external unit may comprise a gyroscope operable to indicate an orientation of a subject and a harness wearable by a subject and operable to align the gyroscope with the subject. The imaging capsule may send and image to an external unit for processing and display, and the external unit may provide for calculation of the image-axis orientation relative to the body.

    摘要翻译: 实施例包括具有图像轴的图像捕获装置和可操作以指示图像轴的取向的陀螺仪的装置。 胶囊内窥镜系统的实施例包括成像胶囊和外部单元。 成像胶囊可以包括具有图像轴的图像捕获装置和可操作以指示图像轴的取向的陀螺仪。 外部单元可以包括陀螺仪,其可操作以指示受试者的方位和由受试者佩戴的线束并可操作以将陀螺仪与对象对准。 成像胶囊可以发送和图像到外部单元进行处理和显示,并且外部单元可以提供相对于身体的图像轴取向的计算。

    NOVEL REGISTER RENAMING SYSTEM USING MULTI-BANK PHYSICAL REGISTER MAPPING TABLE AND METHOD THEREOF
    14.
    发明申请
    NOVEL REGISTER RENAMING SYSTEM USING MULTI-BANK PHYSICAL REGISTER MAPPING TABLE AND METHOD THEREOF 有权
    使用多银行物理寄存器映射表的新型寄存器恢复系统及其方法

    公开(公告)号:US20140122837A1

    公开(公告)日:2014-05-01

    申请号:US14064936

    申请日:2013-10-28

    IPC分类号: G06F9/30

    CPC分类号: G06F9/3012 G06F9/384

    摘要: Embodiments of a processor architecture utilizing multi-bank implementation of physical register mapping table are provided. A register renaming system to correlate architectural registers to physical registers includes a physical register mapping table and a renaming logic. The physical register mapping table has a plurality of entries each indicative of a state of a respective physical register. The mapping table has a plurality of non-overlapping sections each of which having respective entries of the mapping table. The renaming logic is coupled to search a number of the sections of the mapping table in parallel to identify entries that indicate the respective physical registers have a first state. The renaming logic selectively correlates each of a plurality of architectural registers to a respective physical register identified as being in the first state. Methods of utilizing the multi-bank implementation of physical register mapping table are also provided.

    摘要翻译: 提供了利用多库实现物理寄存器映射表的处理器架构的实施例。 将结构寄存器与物理寄存器相关联的寄存器重命名系统包括物理寄存器映射表和重命名逻辑。 物理寄存器映射表具有多个表示每个物理寄存器的状态的条目。 映射表具有多个非重叠部分,每个部分具有映射表的相应条目。 重命名逻辑被耦合以并行地搜索映射表的多个部分以识别指示相应物理寄存器具有第一状态的条目。 重命名逻辑选择性地将多个体系结构寄存器中的每一个相关于被识别为处于第一状态的相应物理寄存器。 还提供了利用多库实现物理寄存器映射表的方法。

    Capsule endoscope
    16.
    发明授权

    公开(公告)号:US10883828B2

    公开(公告)日:2021-01-05

    申请号:US15645371

    申请日:2017-07-10

    摘要: An embodiment comprises and apparatus having an image capture device with an image axis and a gyroscope operable to indicate the orientation of the image axis. An embodiment of a capsule endoscopy system comprises an imaging capsule and an external unit. The imaging capsule may comprise an image capture device having an image axis and a gyroscope operable to indicate the orientation of the image axis. The external unit may comprise a gyroscope operable to indicate an orientation of a subject and a harness wearable by a subject and operable to align the gyroscope with the subject. The imaging capsule may send and image to an external unit for processing and display, and the external unit may provide for calculation of the image-axis orientation relative to the body.

    Driving permanent magnet motor based on neutral point voltage

    公开(公告)号:US10686392B2

    公开(公告)日:2020-06-16

    申请号:US16259533

    申请日:2019-01-28

    发明人: Rendong Wang

    摘要: The present disclosure is directed to a permanent magnet motor control method and system. A new structure configuration of a permanent magnet motor has a rotor with two or more permanent magnets attached thereon, a stator wound in a “Y” topology with three coils (windings) arranged at 120 degree among one another, and a neutral point of the wound stator wired in a manner that the voltage at the neutral point may be detected in substantially real time. The detected neutral point voltages are analyzed together with the associated vectors of the excitation current provided to the windings of the stator to determine a speed of the rotor. The determined speed of the rotor is used for vector control.

    DEBUGGING SUPPORT UNIT FOR MICROPROCESSOR
    18.
    发明申请

    公开(公告)号:US20190227905A1

    公开(公告)日:2019-07-25

    申请号:US16368742

    申请日:2019-03-28

    IPC分类号: G06F11/36 G06F11/22

    摘要: A debug-enabled processing device includes a processor, a communication transceiver circuit, and a debug support unit. The debug support unit has a plurality of dedicated debug registers to facilitate debugging a software program under execution by the processor. One of the plurality of debug registers is a control register having at least four bits, which are used to enable/disable a plurality of debugging operations. Others of the debug registers include a set of index registers that may be configured to pass data to and from the processor.

    ZERO-OVERHEAD LOOP IN AN EMBEDDED DIGITAL SIGNAL PROCESSOR

    公开(公告)号:US20170344375A1

    公开(公告)日:2017-11-30

    申请号:US15220338

    申请日:2016-07-26

    IPC分类号: G06F9/30 G06F9/38

    摘要: A decoding logic method is arranged to execute a zero-overhead loop in an embedded digital signal processor (DSP). In the method, instruction data is fetched from a memory, and a plurality of instruction tokens, which are derived from the instruction data, are stored in a token buffer. A first portion of one or more instruction tokens from the token buffer are passed to a first decode module, which may be an instruction decode module, and a second portion of the one or more instruction tokens from the token buffer are passed to a second decode module, which may be a loop decode module. The second decode module detects a special loop instruction token, and based on the detection of the special loop instruction token, a loop counter is conditionally tested. Using the first decode module, at least one instruction token of an iterative algorithm is assembled into a single instruction, which is executable in a single execution cycle. Based on the conditional test of the loop counter, the first decode module further assembles a loop branch instruction of the iterative algorithm into the single instruction executable in one execution cycle.

    DEBUGGING SUPPORT UNIT FOR MICROPROCESSOR
    20.
    发明申请

    公开(公告)号:US20170322867A1

    公开(公告)日:2017-11-09

    申请号:US15203659

    申请日:2016-07-06

    IPC分类号: G06F11/36

    摘要: A debug-enabled processing device includes a processor, a communication transceiver circuit, and a debug support unit. The debug support unit has a plurality of dedicated debug registers to facilitate debugging a software program under execution by the processor. One of the plurality of debug registers is a control register having at least four bits, which are used to enable/disable a plurality of debugging operations. Others of the debug registers include a set of index registers that may be configured to pass data to and from the processor.