公开(公告)号：US20220165699A1

公开(公告)日：2022-05-26

申请号：US17522717

申请日：2021-11-09

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Jing-En LUAN

IPC: H01L23/00

Abstract: The present disclosure is directed to semiconductor packages that include a molding compound having at least one raised portion that extends outward from the package. In some embodiments, the semiconductor packages have a plurality of raised portions, and a plurality of conductive layers are on the plurality of raised portions. The plurality of raised portions and the plurality of conductive layers are utilized to mount the semiconductor packages to an external electronic device (e.g., a printed circuit board (PCB), another semiconductor package, an external electrical connection, etc.). In some embodiments, the semiconductor packages have a single raised portion with a plurality of conductive layers that are on the single raised portion. The single raised portion and the plurality of conductive layers are utilized to mount the semiconductor packages to the external electronic device. The plurality of conductive layers on the plurality of raised portions or the single raised portion may be formed by a laser direct structuring (LDS) process.

公开(公告)号：US20220122941A1

公开(公告)日：2022-04-21

申请号：US17483076

申请日：2021-09-23

Applicant: STMicroelectronics PTE LTD

Inventor： Chun Yi TENG ,  David GANI

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/78

Abstract: Trenches are opened from a top surface of a production wafer that extend down through scribe areas to a depth that is only partially through a semiconductor substrate. Prior to performing a bumping process, a first handle is attached to the top surface of the production wafer. A back surface of the semiconductor substrate is then thinned to reach the trenches and form a wafer level chip scale package at each integrated circuit location delimited by the trenches. A second handle is then attached to a bottom surface of the thinned semiconductor substrate, and the first handle is removed to expose underbump metallization pads at the top surface. The bumping process is then performed to form a solder ball at each of the exposed underbump metallization pads.

公开(公告)号：US11257679B2

公开(公告)日：2022-02-22

申请号：US16690673

申请日：2019-11-21

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Tien Choy Loh

IPC: H01L21/3065 ,  H01L21/02 ,  H01L21/67

Abstract: One or more embodiments are directed to methods of removing a sacrificial layer from semiconductor wafers during wafer processing. In at least one embodiment, the sacrificial layer is removed from a wafer during an O2 plasma etch step. In one embodiment, the sacrificial layer is poly(p-phenylene-2, 6-benzobisoxazole) (PBO) or polyimide. The O2 plasma etch step causes a residue to form on the wafer. The residue is removed by immersing the wafer a solution that is a mixture of the tetramethylammonium hydroxide (TMAH) and water.

公开(公告)号：US11211254B2

公开(公告)日：2021-12-28

申请号：US17096434

申请日：2020-11-12

Applicant: STMicroelectronics Pte Ltd

Inventor： Yuzhan Wang ,  Pradeep Basavanahalli Kumarswamy ,  Hong Kia Koh ,  Alberto Leotti ,  Patrice Ramonda

IPC: H01L21/3105 ,  H01L21/762 ,  H01L21/768

Abstract: A first dielectric layer made of a first dielectric material is deposited over a semiconductor substrate. A buffer layer is then deposited on an upper surface of the first dielectric layer. A trench is opened to extend through the buffer layer and the first dielectric layer. A second dielectric layer made of a second dielectric material is the deposited in a conformal manner on the buffer layer and filling the trench. Chemical mechanical polishing of the second dielectric layer is performed to remove overlying portions of the second dielectric layer with the buffer layer being used as a polish stop. After removing the buffer layer, the first dielectric layer and the second dielectric material filling the trench form a pre-metallization dielectric layer having a substantially planar upper surface.

公开(公告)号：US20210382197A1

公开(公告)日：2021-12-09

申请号：US17411948

申请日：2021-08-25

Applicant: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED ,  STMICROELECTRONICS PTE LTD

Inventor： Wing Shenq WONG ,  Andy PRICE ,  Eric CHRISTISON

IPC: G01V8/12 ,  H01L25/16 ,  H01L31/167

Abstract: A method for forming a molded proximity sensor with an optical resin lens and the structure formed thereby. A light sensor chip is placed on a substrate, such as a printed circuit board, and a diode, such as a laser diode, is positioned on top of the light sensor chip and electrically connected to a bonding pad on the light sensor chip. Transparent, optical resin in liquid form is applied as a drop over the light sensor array on the light sensor chip as well as over the light-emitting diode. After the optical resin is cured, a molding compound is applied to an entire assembly, after which the assembly is polished to expose the lenses and have a top surface flush with the top surface of the molding compound.

公开(公告)号：US20210376061A1

公开(公告)日：2021-12-02

申请号：US17236149

申请日：2021-04-21

Applicant: STMicroelectronics Pte Ltd

Inventor： Yean Ching YONG

IPC: H01L29/06 ,  H01L29/51 ,  H01L29/78 ,  H01L21/762 ,  H01L21/477

Abstract: An integrated circuit includes a polysilicon region that is doped with a dopant. A portion of the polysilicon region is converted to a polyoxide region which includes un-oxidized dopant ions. A stack of layers overlies over the polyoxide region. The stack of layers includes: a first ozone-assisted sub-atmospheric pressure thermal chemical vapor deposition (O3 SACVD) TEOS layer; and a second O3 SACVD TEOS layer; wherein the first and second O3 SACVD TEOS layers are separated from each other by a dielectric region. A thermally annealing is performed at a temperature which induces outgassing of passivation atoms from the first and second O3 SACVD TEOS layers to migrate to passivate interface charges due to the presence of un-oxidized dopant ions in the polyoxide region.

公开(公告)号：US20210327863A1

公开(公告)日：2021-10-21

申请号：US17360925

申请日：2021-06-28

Applicant: STMICROELECTRONICS PTE LTD

Inventor： David GANI

IPC: H01L25/16 ,  G01S17/04 ,  H01S5/02325 ,  H01L21/768 ,  H01L23/48 ,  H01L31/02 ,  H01L31/167 ,  H01L31/18 ,  H04M1/02

Abstract: Wafer level proximity sensors are formed by processing a silicon substrate wafer and a silicon cap wafer separately, bonding the cap wafer to the substrate wafer, forming an interconnect structure of through-silicon vias within the substrate, and singulating the bonded wafers to yield individually packaged sensors. The wafer level proximity sensor is smaller than a conventional proximity sensor and can be manufactured using a shorter fabrication process at a lower cost. The proximity sensors are coupled to external components by a signal path that includes the through-silicon vias and a ball grid array formed on a lower surface of the silicon substrate. The design of the wafer level proximity sensor passes more light from the light emitter and more light to the light sensor.

公开(公告)号：US11069667B2

公开(公告)日：2021-07-20

申请号：US15087959

申请日：2016-03-31

Applicant: STMicroelectronics Pte Ltd

Inventor： David Gani

IPC: H01L25/16 ,  H01L21/768 ,  H01L23/48 ,  H01L31/02 ,  H01L31/167 ,  H01L31/18 ,  H01S5/022 ,  H04M1/02 ,  G06F3/041 ,  G01S17/04 ,  H01S5/02325

Abstract: Wafer level proximity sensors are formed by processing a silicon substrate wafer and a silicon cap wafer separately, bonding the cap wafer to the substrate wafer, forming an interconnect structure of through-silicon vias within the substrate, and singulating the bonded wafers to yield individually packaged sensors. The wafer level proximity sensor is smaller than a conventional proximity sensor and can be manufactured using a shorter fabrication process at a lower cost. The proximity sensors are coupled to external components by a signal path that includes the through-silicon vias and a ball grid array formed on a lower surface of the silicon substrate. The design of the wafer level proximity sensor passes more light from the light emitter and more light to the light sensor.

公开(公告)号：US10910287B2

公开(公告)日：2021-02-02

申请号：US16270927

申请日：2019-02-08

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Yun Liu ,  David Gani

IPC: H01L23/31 ,  H01L21/78 ,  H01L21/56 ,  H01L21/304 ,  H01L23/00 ,  H01L23/28

Abstract: A semiconductor package having a die with a sidewall protected by molding compound, and methods of forming the same are disclosed. The package includes a die with a first surface opposite a second surface and sidewalls extending between the first and second surfaces. A redistribution layer is formed on the first surface of each die. An area of the first surface of the die is greater than an area of the redistribution layer, such that a portion of the first surface of the die is exposed. When molding compound is formed over the die and the redistribution layer to form a semiconductor package, the molding compound is on the first surface of the die between an outer edge of the redistribution layer and an outer edge of the first surface. The molding compound is also on the sidewalls of the die, which provides protection against chipping or cracking during transport.

公开(公告)号：US20200381320A1

公开(公告)日：2020-12-03

申请号：US16880684

申请日：2020-05-21

Applicant: STMicroelectronics PTE LTD

Inventor： Jing-En LUAN

IPC: H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor device having a channel between active sections or portions of the device is disclosed. An elastic material, such as dielectric or a polymer, is deposited into the channel and cured to increase flexibility and thermal expansion properties of the semiconductor device. The elastic material reduces the thermal and mechanical mismatch between the semiconductor device and the substrate to which the semiconductor device is coupled in downstream processing to improve reliability. The semiconductor device may also include a plurality of channels formed transverse with respect to each other. Some of the channels extend all the way through the semiconductor device, while other channels extend only partially through the semiconductor device.