公开(公告)号：US07035365B2

公开(公告)日：2006-04-25

申请号：US10001712

申请日：2002-03-11

申请人： Hiroshi Takatori ,  James M. Little ,  Scott Chiu

发明人： Hiroshi Takatori ,  James M. Little ,  Scott Chiu

IPC分类号： H04L7/00 ,  H04L7/02

CPC分类号： H04L1/205

摘要： A receiver involved in high-speed data transmission includes a decision system. The decision system calculates a value of an input signal and holds the value as a tentative value. The decision system calculates an error value, amplifies the error value, and holds the amplified error value as a corrected value. The decision system determines whether the amplified error value is within a marginal range. The decision system also determines whether adjacent values to the value indicate the input signal was in transition from a positive to negative state, or a negative to positive state. If the amplified error values is within a marginal range and the input signal was in transition from a positive to negative state, or a negative to positive state, then the decision system overrides the tentative value with the corrected value.

公开(公告)号：US08000674B2

公开(公告)日：2011-08-16

申请号：US11830914

申请日：2007-07-31

申请人： Mohammed Sajid ,  Scott Chiu

发明人： Mohammed Sajid ,  Scott Chiu

IPC分类号： H04B1/10

CPC分类号： H04B1/525 ,  G06K7/0008

摘要： Briefly, in accordance with one or more embodiments, a method and device capable of canceling self-jammer and one or more other interfering signals in an radio frequency identification system or the like is disclosed.

摘要翻译： 简而言之，根据一个或多个实施例，公开了能够在射频识别系统等中抵消自干扰和一个或多个其它干扰信号的方法和装置。

公开(公告)号：US20110138162A1

公开(公告)日：2011-06-09

申请号：US12632919

申请日：2009-12-08

申请人： Scott Chiu ,  Mohamed Arafa

发明人： Scott Chiu ,  Mohamed Arafa

IPC分类号： G06F9/24 ,  G11C7/10 ,  G11C7/00 ,  G06F12/02 ,  G06F1/26

CPC分类号： G11C7/10 ,  G06F1/3275 ,  G06F1/3287 ,  G06F13/1673 ,  G11C5/04 ,  Y02D10/14

摘要： A memory module can include a data buffer having a data bus interface and a dynamic random access memory (DRAM) coupled to the data buffer. The memory module may also include a switch connected in parallel with the data buffer, wherein the switch can selectively bypass the data buffer. In one example, the memory module also includes a registered buffer having an address bus interface, where the switch may selectively bypass the data buffer based on a program signal obtained from an address bus via the address bus interface.

摘要翻译： 存储器模块可以包括具有数据总线接口的数据缓冲器和耦合到数据缓冲器的动态随机存取存储器（DRAM）。 存储器模块还可以包括与数据缓冲器并联连接的开关，其中开关可以有选择地绕过数据缓冲器。 在一个示例中，存储器模块还包括具有地址总线接口的注册缓冲器，其中交换机可以基于经由地址总线接口从地址总线获得的程序信号选择性地旁路数据缓冲器。

公开(公告)号：US07693493B2

公开(公告)日：2010-04-06

申请号：US11771374

申请日：2007-06-29

申请人： Scott Chiu ,  Marc Loyer ,  Thomas J Barnes ,  Rapp Jan ,  Jimmy Carlsson

发明人： Scott Chiu ,  Marc Loyer ,  Thomas J Barnes ,  Rapp Jan ,  Jimmy Carlsson

IPC分类号： H04B1/38

CPC分类号： H03C1/50

摘要： Mechanisms for reducing amplitude-modulated noise in a wireless transceiver are generally described. In one example, an apparatus includes a radio-frequency identification (RFID) transceiver, a digital-analog converter (DAC) coupled with the transceiver, a reconstruction filter coupled with the digital-analog converter, and hold logic associated with the reconstruction filter to enable the reconstruction filter to hold its output voltage.

摘要翻译： 通常描述用于降低无线收发器中的调幅噪声的机制。 在一个示例中，设备包括射频识别（RFID）收发器，与收发器耦合的数模转换器（DAC），与数模转换器耦合的重建滤波器以及与重构滤波器相关联的保持逻辑 使重构滤波器保持其输出电压。

公开(公告)号：US07154979B2

公开(公告)日：2006-12-26

申请号：US10003330

申请日：2002-03-11

申请人： Hiroshi Takatori ,  James M Little ,  Scott Chiu

发明人： Hiroshi Takatori ,  James M Little ,  Scott Chiu

IPC分类号： H03D3/24

CPC分类号： H03L7/093 ,  H03L7/107 ,  H04L7/0083 ,  H04L7/033

摘要： A timing recovery system includes a phase locked loop with a variable bandwidth loop filter, several data dependent gain units, and three proportional paths with non-linear control. The system provides excellent jitter tolerance with a wide variation in data density and large amplitude jitter with a wide frequency range. The gain of both an included loop filter and a phase detector may be varied with both frequency and data density. Direct, unfiltered adjustments may be made to phase based on a received data pattern and phase error magnitude to reduce loop latency and provide temporary and immediate boost in the loop gain of the phase locked loop. Direct, unfiltered adjustments may also be made to phase based on the sign of the first differential of an accumulator output during long strings of zeros to help maintain tracking even with a very low data density.

公开(公告)号：US20050058279A1

公开(公告)日：2005-03-17

申请号：US10664334

申请日：2003-09-17

申请人： Scott Chiu ,  Richard Carruth

发明人： Scott Chiu ,  Richard Carruth

IPC分类号： H04L12/40 ,  H04M1/00 ,  H04M9/00 ,  H04M19/00

CPC分类号： H04L12/40032 ,  H04L12/40 ,  H04M19/001

摘要： In some embodiments, an apparatus includes a line side circuit and a system side circuit to couple to the line side circuit via an isolation interface. The system side circuit includes a first clock line to couple to the line side circuit via a first capacitor to supply a first clock signal to the line side circuit, and a second clock line to couple to the line side circuit via a second capacitor to supply a second clock signal to the line side circuit.

摘要翻译： 在一些实施例中，装置包括线路侧电路和经由隔离接口耦合到线路侧电路的系统侧电路。 系统侧电路包括第一时钟线，用于经由第一电容器耦合到线路侧电路以向线路侧电路提供第一时钟信号，以及第二时钟线，以经由第二电容器耦合到线路侧电路以供应 向线路侧电路施加第二时钟信号。

公开(公告)号：US6014120A

公开(公告)日：2000-01-11

申请号：US668960

申请日：1996-06-24

申请人： Scott Chiu ,  Marlene J. Begay ,  Scott R. Novis ,  John B. Van Zile

发明人： Scott Chiu ,  Marlene J. Begay ,  Scott R. Novis ,  John B. Van Zile

IPC分类号： G09G3/20 ,  G09G3/32

CPC分类号： G09G3/32 ,  G09G2310/02 ,  G09G3/2014

摘要： A method and apparatus includes row-major memory mapping for a graphics memory (14) while providing data to a column-major display such as a pixel array (19). The transfer of data is provided from a row-major memory map to data formatted for refreshing a column-major display. The column-major pixel array (19) provides a display with energy saving benefits for illuminating the LEDs. A software developer can provide graphics data generated or transferred by a microcontroller (12) for storage in the row-major graphics memory (14). The embodiment supports the display features such as the grey-scale mode and bi-level mode.

摘要翻译： 一种方法和装置包括用于图形存储器（14）的行主存储器映射，同时向诸如像素阵列（19）的列主显示器提供数据。 将数据传输从行主存储器映射提供给格式化用于刷新列主显示器的数据。 列主像素阵列（19）为照明LED提供了具有节能优势的显示器。 软件开发人员可以提供由微控制器（12）生成或传送的图形数据，用于存储在行主图形存储器（14）中。 该实施例支持诸如灰度模式和双电平模式的显示特征。

公开(公告)号：US20090003487A1

公开(公告)日：2009-01-01

申请号：US11771374

申请日：2007-06-29

申请人： Scott Chiu ,  Marc Loyer ,  Thomas J. Barnes ,  Jan Rapp ,  Jimmy Carlsson

发明人： Scott Chiu ,  Marc Loyer ,  Thomas J. Barnes ,  Jan Rapp ,  Jimmy Carlsson

IPC分类号： H03C1/52

CPC分类号： H03C1/50

摘要： Mechanisms for reducing amplitude-modulated noise in a wireless transceiver are generally described. In one example, an apparatus includes a radio-frequency identification (RFID) transceiver, a digital-analog converter (DAC) coupled with the transceiver, a reconstruction filter coupled with the digital-analog converter, and hold logic associated with the reconstruction filter to enable the reconstruction filter to hold its output voltage.

摘要翻译： 通常描述用于降低无线收发机中的调幅噪声的机制。 在一个示例中，设备包括射频识别（RFID）收发器，与收发器耦合的数模转换器（DAC），与数模转换器耦合的重建滤波器以及与重构滤波器相关联的保持逻辑 使重构滤波器保持其输出电压。

公开(公告)号：US20070207831A1

公开(公告)日：2007-09-06

申请号：US11241067

申请日：2005-09-30

申请人： Keith Tinsley ,  Scott Chiu

发明人： Keith Tinsley ,  Scott Chiu

IPC分类号： H04M1/00

CPC分类号： G06F13/4004

摘要： Embodiments include systems and methods for integration of RF components onto a single die with functional processing circuitry. For example, one integrated circuit may comprise multiple processors that can communicate there between by way of Radio Frequency (RF) transmission. The processors may also communicate with slave devices by way of radio frequency. Transmission and reception may be at frequencies in a band hitherto unused in computing devices and their peripherals.

摘要翻译： 实施例包括用于将RF组件集成到具有功能处理电路的单个管芯上的系统和方法。 例如，一个集成电路可以包括可以通过射频（RF）传输之间在那里通信的多个处理器。 处理器还可以通过无线电频率与从设备进行通信。 传输和接收可以是在计算设备及其外围设备中迄今使用的频带中的频率。

公开(公告)号：US20070004355A1

公开(公告)日：2007-01-04

申请号：US11172235

申请日：2005-06-29

申请人： Issy Kipnis ,  Scott Chiu ,  David Westberg ,  Jan Rapp ,  Jonas Johansson

发明人： Issy Kipnis ,  Scott Chiu ,  David Westberg ,  Jan Rapp ,  Jonas Johansson

IPC分类号： H04B1/18

CPC分类号： H03D3/008 ,  H03D7/166 ,  H04B1/26 ,  H04B1/30

摘要： Apparatus, system, and method for multi-class wireless receiver are described. The multi-class receiver includes a first down-converter coupled to an input port, a filter coupled to the first-down converter, and a second down-converter coupled to the filter. In a first mode, the filter is configured as a first filter and the second down-converter is disabled. In a second mode, the filter is configured as a second filter and the second down converter is enabled. The system includes a wireless module and a wireless transceiver in communication with the wireless module. The method includes receiving multi-class RF signals, converting at least a first class of RF signals in a first mode of operation, and converting at least a second class of RF signals in a second mode of operation with said multi-class receiver.

摘要翻译： 描述了用于多类无线接收机的装置，系统和方法。 多级接收机包括耦合到输入端口的第一下变频器，耦合到第一下变频器的滤波器和耦合到滤波器的第二下变频器。 在第一模式中，滤波器被配置为第一滤波器并且第二下变频器被禁用。 在第二模式中，滤波器被配置为第二滤波器，并且第二下变频器被使能。 该系统包括与无线模块通信的无线模块和无线收发器。 该方法包括接收多类RF信号，在第一操作模式下转换至少第一类RF信号，并且在所述多级接收机中以第二操作模式转换至少第二类RF信号。