公开(公告)号：US06975974B2

公开(公告)日：2005-12-13

申请号：US09920034

申请日：2001-08-01

Applicant: Chen-Fu Chien ,  Kuo-Hao Chang ,  Chih-Ping Chen ,  Shun-Li Lin

Inventor： Chen-Fu Chien ,  Kuo-Hao Chang ,  Chih-Ping Chen ,  Shun-Li Lin

IPC: G03F7/20 ,  H01L21/66 ,  G06F17/10

CPC classification number: G03F7/705 ,  G03F7/70533 ,  G03F7/70633 ,  H01L22/20

Abstract: In the manufacturing of VLSI circuits, production of overlay is a critical step. To obtain a higher resolution and alignment accuracy in microlithographic process, overlay errors must be measured so that overlay errors can be reduced to a tolerable level. This invention provides an overlay error model and a sampling strategy. Utilizing the overlay model and sampling strategy, a device for measuring overlay errors is also designed.

Abstract translation: 在VLSI电路的制造中，覆盖层的生产是关键的一步。 为了在微光刻工艺中获得更高的分辨率和对准精度，必须测量重叠误差，以便覆盖误差可以降低到可容忍的水平。 本发明提供了重叠误差模型和采样策略。 利用覆盖模型和采样策略，还设计了测量重叠误差的装置。

公开(公告)号：US20060238761A1

公开(公告)日：2006-10-26

申请号：US11112115

申请日：2005-04-21

Applicant: Shun-Li Lin ,  Chen-Fu Chien ,  Chia-Yu Hsu ,  I-Pien Wu

Inventor： Shun-Li Lin ,  Chen-Fu Chien ,  Chia-Yu Hsu ,  I-Pien Wu

IPC: G01B11/00

CPC classification number: G03F7/70633 ,  G03F7/705

Abstract: A method for analyzing overlay errors in lithography is described. Interfield sampling and intrafield sampling are first conducted to sample multiple positions on each of the wafers, and then the overlay error value at each of the positions is measured. An overlay error model including coefficients of intrafield and interfield overlay errors of different types is used to fit the measured overlay error values with respect to the sampled positions. In the overlay error model, the intrafield overlay errors include intrafield translation, isotropic magnification, reticle rotation, asymmetric magnification and asymmetric rotation, and the interfield overlay errors include interfield translation, scale error, wafer rotation and orthogonality error.

公开(公告)号：US07008870B2

公开(公告)日：2006-03-07

申请号：US10707632

申请日：2003-12-26

Applicant: Shun-Li Lin ,  Yun Chu Lin ,  Wen Chung Chang ,  Ching Yi Lee

Inventor： Shun-Li Lin ,  Yun Chu Lin ,  Wen Chung Chang ,  Ching Yi Lee

IPC: H01L21/4763

CPC classification number: H01L21/0276 ,  H01L21/31144 ,  H01L21/76802

Abstract: A structure applied to a photolithographic process is provided. The structure comprises at least a film layer, an optical isolation layer, an anti-reflection coating and a photoresist layer sequentially formed over a substrate. In the photolithographic process, the optical isolation layer stops light from penetrating down to the film layer. Since the optical isolation layer is set up underneath the photoresist layer, light emitted from a light source during photo-exposure is prevented from reflecting from the substrate surface after passing through the film layer. Thus, the critical dimensions of the photolithographic process are unaffected by any change in the thickness of the film layer.

Abstract translation: 提供了应用于光刻工艺的结构。 该结构至少包括在衬底上顺序形成的膜层，光学隔离层，抗反射涂层和光致抗蚀剂层。 在光刻工艺中，光隔离层阻止光穿透到膜层。 由于光隔离层被设置在光致抗蚀剂层的下方，因此防止了在曝光期间从光源发出的光在通过膜层之后从基板表面反射。 因此，光刻工艺的临界尺寸不受膜层厚度的任何变化的影响。

公开(公告)号：US20050003617A1

公开(公告)日：2005-01-06

申请号：US10613817

申请日：2003-07-01

Applicant: Shun-Li Lin ,  Chen-Fu Chien ,  Jing-Feng Deng

Inventor： Shun-Li Lin ,  Chen-Fu Chien ,  Jing-Feng Deng

IPC: G03F1/14 ,  G03F7/00 ,  H01L21/027 ,  H01L21/8234 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/112

CPC classification number: G03F1/36 ,  H01L27/112 ,  H01L27/11253

Abstract: A template padding method for padding edges of at least one hole on a semiconductor mask. The exposure and padding process is modulized. A padding database is developed based on the feature size and the pattern to be exposed. In the method of the present invention, the environment to be exposed is found firstly, and specific exposure module is then searched out. The padding result of the module is pre-found and stored in a database by diffraction operation, such as OPC method. Padding of a hole on a mask about a cell of a wafer can be performed directly by using a value stored. The complicated calculation can be greatly reduced. The method is adjustable according to the feature size of the product and the exposing pattern. The method can be used to random-distribution of holes on a mask surface, so as to determine a padding area effectively.

Abstract translation: 一种用于在半导体掩模上填充至少一个孔的边缘的模板填充方法。 暴露和填充过程被模拟。 基于要暴露的特征尺寸和图案开发填充数据库。 在本发明的方法中，首先找到要暴露的环境，然后搜索特定的曝光模块。 模块的填充结果通过诸如OPC方法的衍射操作预先发现并存储在数据库中。 可以通过使用存储的值来直接执行在晶片的单元周围的掩模上的孔的填充。 复杂的计算可以大大减少。 该方法根据产品的特征尺寸和曝光图案可调。 该方法可以用于掩模表面上的空穴的随机分布，从而有效地确定填充区域。

公开(公告)号：US06627388B2

公开(公告)日：2003-09-30

申请号：US09900579

申请日：2001-07-06

Applicant: Shun-Li Lin ,  Chi-Fang Hsieh

Inventor： Shun-Li Lin ,  Chi-Fang Hsieh

IPC: G03F740

CPC classification number: G03F7/40

Abstract: The invention provides a method for reducing roughness of the photoresist through cross-linking reaction of deposit and the photoresist. The method comprises at least performing an exposure process to a substrate having a photoresist pattern and performing a post-exposure bake process for activating the surface of photoresist pattern. A material layer is formed to cover the surface of the photoresist pattern. The material layer cross-links with the hydrogen ions on the surface of the photoresist pattern, so that a filling layer is formed to fills asperity or the rough regions of the photoresist pattern.

公开(公告)号：US06348384B1

公开(公告)日：2002-02-19

申请号：US09899141

申请日：2001-07-06

Applicant: Shun Li Lin

Inventor： Shun Li Lin

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/2652

Abstract: The present invention provides a method of using organic polymer as a covering layer for a device lightly doped drain (LDD) structure, wherein a photo resist is covered by organic polymer, and ion implantation of different energies and kinds are performed to the same region of different line widths, thereby achieving the effect of LDD. Additionally, the covering layer of organic polymer is removed by means of simple and easy oxygen plasma etch so as not to increase the complexity of fabrication process. The complex fabrication process of a device LDD structure in the prior art is thus greatly improved.

Abstract translation: 本发明提供一种使用有机聚合物作为轻掺杂漏极（LDD）器件的覆盖层的方法，其中光致抗蚀剂被有机聚合物覆盖，并且将不同能量和种类的离子注入执行到 不同的线宽，从而达到LDD的效果。 此外，通过简单且容易的氧等离子体蚀刻来去除有机聚合物的覆盖层，从而不增加制造工艺的复杂性。 因此，现有技术中的器件LDD结构的复杂制造工艺大大改进。