公开(公告)号：US09317891B2

公开(公告)日：2016-04-19

申请号：US13913206

申请日：2013-06-07

Applicant: Anita Chowdhry ,  Subir Ghosh

Inventor： Anita Chowdhry ,  Subir Ghosh

IPC: G09G5/36 ,  G06T1/60 ,  G09G5/393 ,  G09G5/39

CPC classification number: G06T1/60 ,  G09G5/39 ,  G09G5/393

Abstract: Systems and methods for hardware-accelerated key color extraction are disclosed. An update corresponding to a portion of a digital representation of a display screen is received. Key color information for locations within the update is identified. A data structure code associated with the portion of the digital representation of the display screen is determined based on the identification of the key color information. The data structure code is provided to a data structure. During a scan of the frame buffer for display, the frame buffer is capable of being read according to the data structure.

Abstract translation: 公开了用于硬件加速键颜色提取的系统和方法。 接收对应于显示屏幕的数字表示的一部分的更新。 识别更新中位置的关键颜色信息。 基于键颜色信息的识别来确定与显示屏幕的数字表示的部分相关联的数据结构代码。 数据结构代码被提供给数据结构。 在用于显示的帧缓冲器的扫描期间，帧缓冲器能够根据数据结构进行读取。

公开(公告)号：US08907987B2

公开(公告)日：2014-12-09

申请号：US12908365

申请日：2010-10-20

Applicant: Anita Chowdhry ,  Subir Ghosh

Inventor： Anita Chowdhry ,  Subir Ghosh

IPC: G09G5/00 ,  G06T3/40 ,  G09G5/36 ,  H04N7/01 ,  G09G5/14 ,  G09G5/393 ,  G09G5/395 ,  G09G5/397

CPC classification number: G09G5/14 ,  G09G5/393 ,  G09G5/395 ,  G09G5/397 ,  G09G2340/02 ,  G09G2340/0407 ,  G09G2350/00 ,  G09G2360/18 ,  G09G2370/022

Abstract: The video output system in a computer system reads pixel information from a frame buffer to generate a video output signal. In addition, full-motion video may also be displayed in a window defined in the frame buffer. If the native resolution of the full-motion video is larger than the window defined in said frame buffer then valuable memory space and memory bandwidth is being wasted by writing said larger full-motion video in a memory system (and later reading it back) when some data from the full-motion video will be discarded. Thus, a video pre-processor is disclosed to reduce the size of the full-motion video before that full-motion video is written into a memory system. The video pre-processor will scale the full-motion video down to a size no larger than the window defined in the frame buffer.

Abstract translation: 计算机系统中的视频输出系统从帧缓冲器读取像素信息以产生视频输出信号。 此外，全动态视频也可以在帧缓冲器中定义的窗口中显示。 如果全动态视频的原始分辨率大于在所述帧缓冲器中定义的窗口，则通过将较大的全运动视频写入存储器系统（并稍后读回）来浪费宝贵的存储器空间和存储器带宽，当时 来自全动态视频的一些数据将被丢弃。 因此，公开了一种视频预处理器，用于在将全动态视频写入存储器系统之前减小全动态视频的尺寸。 视频预处理器将把全动态视频缩小至不大于帧缓冲区中定义的窗口的大小。

公开(公告)号：US08891545B2

公开(公告)日：2014-11-18

申请号：US13499545

申请日：2010-10-01

Applicant: Gabriele Sartori ,  Subir Ghosh ,  Nikolay Kovach

Inventor： Gabriele Sartori ,  Subir Ghosh ,  Nikolay Kovach

IPC: H04L12/28 ,  G09G5/12 ,  H04N7/083

CPC classification number: G09G5/12 ,  G09G2370/022 ,  H04N7/083

Abstract: Thin-client terminal systems allow computer systems to be shared by multiple computer users. With modern technology, the cost of implementing a thin-client terminal system can be very low. To improve thin-client terminal systems, a thin-client terminal system accepts user input data in a first serial interface format and transcodes the user input data into a second serial interface format for transmission to a server.

Abstract translation: 瘦客户机终端系统允许计算机系统由多个计算机用户共享。 利用现代技术，实现瘦客户端终端系统的成本可能非常低。 为了改进瘦客户机终端系统，瘦客户机终端系统以第一串行接口格式接受用户输入数据，并将用户输入数据转码为第二串行接口格式以传输到服务器。

公开(公告)号：US08800017B2

公开(公告)日：2014-08-05

申请号：US12474681

申请日：2009-05-29

Applicant: Subir Ghosh ,  Gabriele Sartori

Inventor： Subir Ghosh ,  Gabriele Sartori

IPC: H04L9/32

CPC classification number: H04L9/3234 ,  H04L2209/605

Abstract: A device and a method of authenticating an electronic device are described. The method may comprise transmitting a token value and a parameter value to the electronic device and selecting a private key within the electronic device using the parameter value. The token value may be processed with a method selected by the parameter value to generate a processed token. The processed token may be compared with an expected processed token and the electronic device may be authenticated if the processed token compares favorably with said expected processed token.

Abstract translation: 描述了一种认证电子设备的设备和方法。 该方法可以包括向电子设备发送令牌值和参数值，并使用参数值选择电子设备内的私钥。 可以使用由参数值选择的方法来处理令牌值，以生成已处理的令牌。 处理的令牌可以与预期处理的令牌进行比较，并且如果所处理的令牌与所述预期处理的令牌相比较，则电子设备可被认证。

公开(公告)号：US20120219070A1

公开(公告)日：2012-08-30

申请号：US13499516

申请日：2010-10-01

Applicant: Gabriele Sartori ,  Subir Ghosh ,  William Liao

Inventor： Gabriele Sartori ,  Subir Ghosh ,  William Liao

IPC: H04N7/26 ,  G06F15/16 ,  G06F13/14

CPC classification number: G06F13/385 ,  G06F2213/3812

Abstract: In a system and method for a thin-client terminal system having a local screen buffer using a serial bus, a serial bus interface device receives encoded data from a thin-client server system. The serial bus interface device decodes the encoded data according to a serial bus data format and provides the decoded data to a thin-client control system. The thin-client control system distributes the decoded data for processing to a video processing system, an audio processing system, and an input/output control system. The thin-client control system also receives input data from input devices connected to the thin-client terminal system. The input data is processed and encoded according to the serial bus data format for transmission to the thin-client server system.

Abstract translation: 在具有使用串行总线的本地屏幕缓冲器的瘦客户机终端系统的系统和方法中，串行总线接口设备从瘦客户端服务器系统接收编码数据。 串行总线接口设备根据串行总线数据格式解码编码数据，并将解码的数据提供给瘦客户端控制系统。 瘦客户端控制系统将用于处理的解码数据分配给视频处理系统，音频处理系统和输入/输出控制系统。 瘦客户端控制系统还从连接到瘦客户机终端系统的输入设备接收输入数据。 输入数据根据串行总线数据格式进行处理和编码，以传输到瘦客户端服务器系统。

公开(公告)号：US08248425B2

公开(公告)日：2012-08-21

申请号：US12560990

申请日：2009-09-16

Applicant: Subir Ghosh

Inventor： Subir Ghosh

IPC: G06F13/00

CPC classification number: G06F13/00 ,  G06F3/1423 ,  G09G5/18 ,  G09G5/395 ,  G09G2350/00 ,  G09G2370/022

Abstract: Graphics display adapters for driving multiple display monitors have become very popular. Graphics display adapters that drive multiple monitors can be used to provide terminal services to multiple independent terminals or be used to provide multiple displays to a single user. Generating video signals for multiple display systems puts a heavy burden on the video memory system since multiple different video signal generators may read from associated frame buffers in a shared video memory system. In one disclosed embodiment, a plurality of video memory read triggers are provided wherein at least two of which are staggered to reduce the load on the video memory system. In response to each read trigger, display data is read from a frame buffer to an associated video signal generation circuit. Each video signal generation circuit then provides a display signal to an associated display screen in a multi-screen environment.

Abstract translation: 用于驱动多个显示器的图形显示适配器变得非常受欢迎。 用于驱动多个显示器的图形显示适配器可用于向多个独立终端提供终端服务，或用于向单个用户提供多个显示。 为多个显示系统生成视频信号给视频存储系统带来沉重的负担，因为多个不同的视频信号发生器可以从共享视频存储器系统中的相关联的帧缓冲器中读取。 在一个公开的实施例中，提供了多个视频存储器读取触发器，其中至少两个交错地交错以减少视频存储器系统上的负载。 响应于每个读取触发，将显示数据从帧缓冲器读取到相关联的视频信号生成电路。 然后，每个视频信号发生电路在多屏幕环境中向相关的显示屏提供显示信号。

公开(公告)号：US20120120320A1

公开(公告)日：2012-05-17

申请号：US12947294

申请日：2010-11-16

Applicant: Anita Chowdhry ,  Subir Ghosh

Inventor： Anita Chowdhry ,  Subir Ghosh

IPC: H04N9/74 ,  G09G5/36

CPC classification number: H04N9/75 ,  G06F3/14 ,  G06F3/1415 ,  G06F3/1454 ,  G09G5/026 ,  G09G5/14 ,  G09G5/397 ,  G09G2320/10 ,  G09G2340/02 ,  G09G2340/125 ,  G09G2350/00 ,  G09G2360/10 ,  G09G2360/125 ,  G09G2370/022

Abstract: The video output system in a computer system reads pixel information from a frame buffer to generate a video output signal. In addition, a full-motion video may also be displayed. Reading from both the frame buffer and the full-motion video buffer when displaying the full-motion video window wastes valuable memory bandwidth. Thus, the disclosed system provides a system and methods for identifying where the video output system must read from the frame buffer and where it must read from the full-motion video buffer while minimizing the amount of area it reads from both the frame buffer and the full-motion video buffer.

Abstract translation: 计算机系统中的视频输出系统从帧缓冲器读取像素信息以产生视频输出信号。 此外，还可以显示全动态视频。 当显示全动态视频窗口时，从帧缓冲器和全动态视频缓冲器读取浪费宝贵的存储器带宽。 因此，所公开的系统提供了一种系统和方法，用于识别视频输出系统必须从帧缓冲器读取的位置以及其必须从全运动视频缓冲器读取的位置，同时最小化其从帧缓冲器和 全动态视频缓冲。

公开(公告)号：US06405291B1

公开(公告)日：2002-06-11

申请号：US09631564

申请日：2000-08-02

Applicant: Subir Ghosh ,  Hsu-Tien Tung

Inventor： Subir Ghosh ,  Hsu-Tien Tung

IPC: G06F1328

CPC classification number: G06F12/0835 ,  G06F12/0862

Abstract: When a PCI-bus controller receives a request from a PCI-bus master to transfer data with an address in secondary memory, the controller performs an initial inquire cycle and withholds TRDY# to the PCI-bus master until any write-back cycle completes. The controller then allows the burst access to take place between secondary memory and the PCI-bus master, and simultaneously and predictively, performs an inquire cycle of the L1 cache for the next cache line. In this manner, if the PCI burst continues past the cache line boundary, the new inquire cycle will already have taken place, or will already be in progress, thereby allowing the burst to proceed with, at most, a short delay. Predictive snoop cycles are not performed if the first transfer of a PCI-bus master access would be the last transfer before a cache line boundary is reached.

Abstract translation: 当PCI总线控制器接收到来自PCI总线主机的请求以在二级存储器中的地址传输数据时，控制器执行初始查询周期，并将TRDY＃保留到PCI总线主机，直到任何回写周期完成。 然后，控制器允许在辅助存储器和PCI总线主机之间进行脉冲串访问，并且同时且预测地执行用于下一个高速缓存线的L1高速缓存的查询周期。 以这种方式，如果PCI突发持续超过高速缓存线边界，则新的查询周期将已经发生或已经在进行，从而允许突发进行至多短暂的延迟。 如果PCI总线主机访问的第一次传输将是达到高速缓存行边界之前的最后一次传输，则不执行预测侦听周期。

公开(公告)号：US4777457A

公开(公告)日：1988-10-11

申请号：US77986

申请日：1987-07-27

Applicant: Subir Ghosh ,  Aluizio Prata, Junior

Inventor： Subir Ghosh ,  Aluizio Prata, Junior

IPC: H01P1/16 ,  H01P1/213 ,  H01P5/12 ,  H01P5/18

CPC classification number: H01P1/213

Abstract: A directional coupler is provided which has an appropriately dimensioned principle waveguide with a frequency dependent reactive boundary interior surface such that the principle waveguide is suitable to simultaneously: (i) support, without depolarization, effective propagation of first signals in a high frequency band at a HE11 mode with greater concentration of energy near the axis of the principle waveguide than near the interior surface and no effective propagation of first signals at any unwanted mode, and (ii) support, without depolarization, effective propagation of second signals in a lower frequency band at a EH11 mode having a greater concentration of energy near the interior surface of the principle waveguide than near the axis and no effective propagation of second signals at any unwanted mode. Four identical secondary waveguides are placed symmetrically at equal radial intervals about the outside perimeter of the principle waveguide with the longitudinal axis of each of the secondary waveguides running parallel to the longitudinal axis of the principle waveguide. A plurality of coupling units are disposed at longitudinal intervals along the principle waveguide with each coupling unit comprising four aperture-like structures interconnecting a respective one of the secondary waveguides and the principle waveguide for exchanging energy in the first signals between the secondary waveguides and the principle waveguide. This structure provides a directional coupler for separation of signals in the first and second frequency bands while preserving their polarization characteristics.

Abstract translation: 提供了一种定向耦合器，其具有适当尺寸的具有频率依赖的反应边界内表面的原理波导，使得主波导适合于同时：（i）支持而不去极化，在第一信号在高频带中的有效传播 HE11模式，在原理波导的轴线附近具有更靠近内部表面的能量集中的能量，并且在任何不需要的模式下无法有效地传播第一信号，以及（ii）支持没有去极化的第二信号在较低频带中的有效传播 在EH11模式下，在原理波导的内表面附近具有比在轴附近更高的能量集中，并且在任何不想要的模式下没有有效地传播第二信号。 四个相同的次级波导以相等的径向间隔围绕主波导的外周对称地放置，其中每个次级波导的纵向轴线平行于主波导的纵向轴线延伸。 多个耦合单元沿着主波导以纵向间隔设置，每个耦合单元包括将相应的一个次级波导和主波导相互连接的四个孔状结构，用于在次级波导之间的第一信号中的能量交换和原理 波导。 该结构提供了一种定向耦合器，用于分离第一和第二频带中的信号，同时保持它们的极化特性。

公开(公告)号：US10733350B1

公开(公告)日：2020-08-04

申请号：US16375684

申请日：2019-04-04

Applicant: Sharat C Prasad ,  Subir Ghosh

Inventor： Sharat C Prasad ,  Subir Ghosh

IPC: G06F17/50 ,  G06F30/392 ,  H04L12/24 ,  G06N5/02 ,  G06N7/00 ,  G06F9/48 ,  G06F30/33

Abstract: A chip design environment is disclosed which accepts application specific processing, memory and IO elements and declarative specification of function, cost and performance of peripheral, low-level and infrastructural elements and of overall design and generates synthesizable module RTLs and relevant place-and-route constraints. The generated elements include the network interconnecting all the elements, a programming memory consistency model and its coherence protocol, allocation and scheduling processes realizing run-time inference of optimal parallel execution and processes for control of coherence action and prefetch intensity, task-data migration, voltage-frequency scaling and power-clock gating. The environment employs knowledge bases, models to predict performance and to assign confidence scores to predictions and, in turn, the predictions to explore space of topology, architecture, composition, etc options. The environment generates synthesizable module RTLs to complete the design and relevant place-and-route constraints. User may simulate the synthesized design. If a user shares simulation results, the environment may evaluate the predicted performance against performance determined by simulation and use the results to update its knowledge and models.