公开(公告)号：US10733350B1

公开(公告)日：2020-08-04

申请号：US16375684

申请日：2019-04-04

Applicant: Sharat C Prasad ,  Subir Ghosh

Inventor： Sharat C Prasad ,  Subir Ghosh

IPC: G06F17/50 ,  G06F30/392 ,  H04L12/24 ,  G06N5/02 ,  G06N7/00 ,  G06F9/48 ,  G06F30/33

Abstract: A chip design environment is disclosed which accepts application specific processing, memory and IO elements and declarative specification of function, cost and performance of peripheral, low-level and infrastructural elements and of overall design and generates synthesizable module RTLs and relevant place-and-route constraints. The generated elements include the network interconnecting all the elements, a programming memory consistency model and its coherence protocol, allocation and scheduling processes realizing run-time inference of optimal parallel execution and processes for control of coherence action and prefetch intensity, task-data migration, voltage-frequency scaling and power-clock gating. The environment employs knowledge bases, models to predict performance and to assign confidence scores to predictions and, in turn, the predictions to explore space of topology, architecture, composition, etc options. The environment generates synthesizable module RTLs to complete the design and relevant place-and-route constraints. User may simulate the synthesized design. If a user shares simulation results, the environment may evaluate the predicted performance against performance determined by simulation and use the results to update its knowledge and models.

公开(公告)号：US08471860B2

公开(公告)日：2013-06-25

申请号：US13548535

申请日：2012-07-13

Applicant: Subir Ghosh

Inventor： Subir Ghosh

IPC: G06F13/00

CPC classification number: G06F13/00 ,  G06F3/1423 ,  G09G5/18 ,  G09G5/395 ,  G09G2350/00 ,  G09G2370/022

Abstract: Graphics display adapters for driving multiple display monitors have become very popular. Graphics display adapters that drive multiple monitors can be used to provide terminal services to multiple independent terminals or be used to provide multiple displays to a single user. Generating video signals for multiple display systems puts a heavy burden on the video memory system since multiple different video signal generators may read from associated frame buffers in a shared video memory system. In one disclosed embodiment, a plurality of video memory read triggers are provided wherein at least two of which are staggered to reduce the load on the video memory system. In response to each read trigger, display data is read from a frame buffer to an associated video signal generation circuit. Each video signal generation circuit then provides a display signal to an associated display screen in a multi-screen environment.

Abstract translation: 用于驱动多个显示器的图形显示适配器变得非常受欢迎。 用于驱动多个显示器的图形显示适配器可用于向多个独立终端提供终端服务，或用于向单个用户提供多个显示。 为多个显示系统生成视频信号给视频存储系统带来沉重的负担，因为多个不同的视频信号发生器可以从共享视频存储器系统中的相关联的帧缓冲器中读取。 在一个公开的实施例中，提供了多个视频存储器读取触发器，其中至少两个交错地交错以减少视频存储器系统上的负载。 响应于每个读取触发，将显示数据从帧缓冲器读取到相关联的视频信号生成电路。 然后，每个视频信号发生电路在多屏幕环境中向相关的显示屏提供显示信号。

公开(公告)号：US20120127185A1

公开(公告)日：2012-05-24

申请号：US13301429

申请日：2011-11-21

Applicant: Anita Chowdhry ,  Subir Ghosh

Inventor： Anita Chowdhry ,  Subir Ghosh

IPC: G09G5/39

CPC classification number: G09G5/393 ,  G06F3/14 ,  G06F3/1415 ,  G06F3/1454 ,  G09G5/026 ,  G09G5/14 ,  G09G5/397 ,  G09G2320/10 ,  G09G2340/02 ,  G09G2340/125 ,  G09G2350/00 ,  G09G2360/10 ,  G09G2360/125 ,  G09G2370/022

Abstract: A video output system in a computer system reads pixel information from a frame buffer to generate a video output signal. In addition, a full-motion video may also be displayed. Reading from both the frame buffer and the full-motion video buffer when displaying the full-motion video window wastes valuable memory bandwidth. Thus, the disclosed system provides a system and methods for identifying where the video output system must read from the frame buffer and where it must read from the full-motion video buffer while minimizing the amount of area it reads from both the frame buffer and the full-motion video buffer.

Abstract translation: 计算机系统中的视频输出系统从帧缓冲器读取像素信息以产生视频输出信号。 此外，还可以显示全动态视频。 当显示全动态视频窗口时，从帧缓冲器和全动态视频缓冲器读取浪费宝贵的存储器带宽。 因此，所公开的系统提供了一种系统和方法，用于识别视频输出系统必须从帧缓冲器读取的位置以及其必须从全运动视频缓冲器读取的位置，同时最小化其从帧缓冲器和 全动态视频缓冲。

公开(公告)号：US20110080519A1

公开(公告)日：2011-04-07

申请号：US12861217

申请日：2010-08-23

Applicant: Anita Chowdhry ,  Subir Ghosh

Inventor： Anita Chowdhry ,  Subir Ghosh

IPC: H04N11/20 ,  H04N9/64

CPC classification number: H04N19/59 ,  H04N19/115 ,  H04N19/156 ,  H04N19/162 ,  H04N19/40 ,  H04N19/44 ,  H04N19/587

Abstract: In a digital video processing system for processing full-motion video in computer terminal systems, two main rendering paths are created for a computer terminal system: a screen buffer path and a full-motion video path. The screen buffer path renders a desktop display from a screen buffer within the terminal system. The full-motion video path decodes a video stream and then processes the decoded video stream with a video processing pipeline to fit the video frames within a destination video window within the desktop display. The video processing pipeline performs clipping, blending, chroma resampling, resizing, and color converting of the video frames in pipelined stages with minimal memory accesses. A video adapter then combines the desktop display with the processed digital video for a final terminal display.

Abstract translation: 在用于在计算机终端系统中处理全运动视频的数字视频处理系统中，为计算机终端系统创建两个主要渲染路径：屏幕缓冲路径和全动态视频路径。 屏幕缓冲路径从终端系统内的屏幕缓冲区呈现桌面显示。 全动态视频路径解码视频流，然后用视频处理流水线处理解码的视频流，以适应桌面显示内的目的地视频窗口内的视频帧。 视频处理流水线以最小的存储器访问在流水线阶段中执行剪辑，混合，色度重采样，调整大小和颜色转换。 然后，视频适配器将桌面显示器与处理后的数字视频相结合，用于最终终端显示。

公开(公告)号：US20110063315A1

公开(公告)日：2011-03-17

申请号：US12560990

申请日：2009-09-16

Applicant: Subir Ghosh

Inventor： Subir Ghosh

IPC: G06F13/00

CPC classification number: G06F13/00 ,  G06F3/1423 ,  G09G5/18 ,  G09G5/395 ,  G09G2350/00 ,  G09G2370/022

Abstract: Graphics display adapters for driving multiple display monitors have become very popular. Graphics display adapters that drive multiple monitors can be used to provide terminal services to multiple independent terminals or be used to provide multiple displays to a single user. Generating video signals for multiple display systems puts a heavy burden on the video memory system since multiple different video signal generators may read from associated frame buffers in a shared video memory system. In one disclosed embodiment, a plurality of video memory read triggers are provided wherein at least two of which are staggered to reduce the load on the video memory system. In response to each read trigger, display data is read from a frame buffer to an associated video signal generation circuit. Each video signal generation circuit then provides a display signal to an associated display screen in a multi-screen environment.

Abstract translation: 用于驱动多个显示器的图形显示适配器变得非常受欢迎。 用于驱动多个显示器的图形显示适配器可用于向多个独立终端提供终端服务，或用于向单个用户提供多个显示。 为多个显示系统生成视频信号给视频存储系统带来沉重的负担，因为多个不同的视频信号发生器可以从共享视频存储器系统中的相关联的帧缓冲器中读取。 在一个公开的实施例中，提供了多个视频存储器读取触发器，其中至少两个交错地交错以减少视频存储器系统上的负载。 响应于每个读取触发，将显示数据从帧缓冲器读取到相关联的视频信号生成电路。 然后，每个视频信号发生电路在多屏幕环境中向相关的显示屏提供显示信号。

公开(公告)号：US09161063B2

公开(公告)日：2015-10-13

申请号：US12395152

申请日：2009-02-27

Applicant: Subir Ghosh ,  Gabriele Sartori

Inventor： Subir Ghosh ,  Gabriele Sartori

IPC: G09G5/00 ,  H04N21/2343 ,  H04N21/443 ,  G06F17/30 ,  H04N19/70 ,  H04N21/235 ,  H04N21/41 ,  H04N21/426 ,  H04N21/45 ,  H04N21/454 ,  H04N21/462

CPC classification number: H04N19/40 ,  G06F17/30905 ,  H04N19/48 ,  H04N19/70 ,  H04N21/234309 ,  H04N21/2358 ,  H04N21/4113 ,  H04N21/4122 ,  H04N21/42607 ,  H04N21/42653 ,  H04N21/443 ,  H04N21/4516 ,  H04N21/454 ,  H04N21/4621

Abstract: A digital video transmission system that operates with three different video rendering paths. A first rendering path operates by receiving display requests and rendering bit-mapped graphics in a local screen buffer. The display information in that local screen buffer is then encoded and transmitted to a remote display system that recreates the content of that local screen buffer in a video buffer of remote display system. A second rendering path operates by receiving encoded video stream requests that can be decoded by the remote display system. Such encoded video streams are sent to the remote display system with minimal addition transport encoding. The third rendering path handles encoded video streams that cannot be handled natively by the remote display system. Such video streams may be either transcoded before transmission or decoded and stored within the local screen buffer.

Abstract translation: 一种以三种不同的视频渲染路径运行的数字视频传输系统。 第一渲染路径通过在本地屏幕缓冲器中接收显示请求和渲染位映射图形来操作。 然后将该本地屏幕缓冲器中的显示信息编码并发送到在远程显示系统的视频缓冲器中重建该本地屏幕缓冲器的内容的远程显示系统。 第二渲染路径通过接收可由远程显示系统解码的编码视频流请求来操作。 这种编码的视频流以最小的附加传输编码被发送到远程显示系统。 第三个渲染路径处理无法由远程显示系统本机处理的编码视频流。 这样的视频流可以在传输之前进行转码或解码并存储在本地屏幕缓冲器中。

公开(公告)号：US08896612B2

公开(公告)日：2014-11-25

申请号：US12947294

申请日：2010-11-16

Applicant: Anita Chowdhry ,  Subir Ghosh

Inventor： Anita Chowdhry ,  Subir Ghosh

IPC: G09G5/36 ,  G09G5/397 ,  H04N9/75 ,  G06F3/14 ,  G09G5/14 ,  G09G5/02

CPC classification number: H04N9/75 ,  G06F3/14 ,  G06F3/1415 ,  G06F3/1454 ,  G09G5/026 ,  G09G5/14 ,  G09G5/397 ,  G09G2320/10 ,  G09G2340/02 ,  G09G2340/125 ,  G09G2350/00 ,  G09G2360/10 ,  G09G2360/125 ,  G09G2370/022

Abstract: The video output system in a computer system reads pixel information from a frame buffer to generate a video output signal. In addition, a full-motion video may also be displayed. Reading from both the frame buffer and the full-motion video buffer when displaying the full-motion video window wastes valuable memory bandwidth. Thus, the disclosed system provides a system and methods for identifying where the video output system must read from the frame buffer and where it must read from the full-motion video buffer while minimizing the amount of area it reads from both the frame buffer and the full-motion video buffer.

Abstract translation: 计算机系统中的视频输出系统从帧缓冲器读取像素信息以产生视频输出信号。 此外，还可以显示全动态视频。 当显示全动态视频窗口时，从帧缓冲器和全动态视频缓冲器读取浪费宝贵的存储器带宽。 因此，所公开的系统提供了一种系统和方法，用于识别视频输出系统必须从帧缓冲器读取的位置以及其必须从全运动视频缓冲器读取的位置，同时最小化其从帧缓冲器和 全动态视频缓冲。

公开(公告)号：US5813036A

公开(公告)日：1998-09-22

申请号：US851666

申请日：1997-05-06

Applicant: Subir Ghosh ,  Hsu-Tien Tung

Inventor： Subir Ghosh ,  Hsu-Tien Tung

IPC: G06F12/08 ,  G06F13/28

CPC classification number: G06F12/0835 ,  G06F12/0862

Abstract: When a PCI-bus controller receives a request from a PCI-bus master to transfer data with an address in secondary memory, the controller performs an initial inquire cycle and withholds TRDY# to the PCI-bus master until any write-back cycle completes. The controller then allows the burst access to take place between secondary memory and the PCI-bus master, and simultaneously and predictively, performs an inquire cycle of the L1 cache for the next cache line. In this manner, if the PCI burst continues past the cache line boundary, the new inquire cycle will already have taken place, or will already be in progress, thereby allowing the burst to proceed with, at most, a short delay. Predictive snoop cycles are not performed if the first transfer of a PCI-bus master access would be the last transfer before a cache line boundary is reached.

公开(公告)号：US4922213A

公开(公告)日：1990-05-01

申请号：US255637

申请日：1988-10-11

Applicant: Subir Ghosh

Inventor： Subir Ghosh

IPC: H01P1/165 ,  H01Q15/24

CPC classification number: H01Q15/24 ,  H01P1/165

Abstract: A polarizer has a plurality of short waveguide sections arranged so that rectangular-shaped sections alternate with circular-shaped sections. The two end sections are both circular. The rectangular sections have a minimum size at least as large as the minimum diameter of the circular sections. The size of the rectangular sections progressively changes from section to section with all sections of the polarizer being symmetrical about the centre point of the polarizer. The length of each section is less than half a wavelength at maximum operating frequency. The structure of the polarizer is simple and straightforward so that computer-aided analysis and design methods can easily be used. The polarizer has a relatively large bandwidth and can interface directly with corrugated circular waveguides.

Abstract translation: 偏振器具有多个短波导部分，其布置成使得矩形部分与圆形部分交替。 两个端部都是圆形的。 矩形截面具有至少与圆形截面的最小直径一样大的最小尺寸。 矩形部分的尺寸逐渐变化，偏振片的所有部分都围绕偏振片的中心点对称。 每个部分的长度在最大工作频率下小于波长的一半。 偏振器的结构简单直观，可以方便地使用计算机辅助分析和设计方法。 偏振器具有相对较大的带宽并且可以直接与波形圆形波导接合。

公开(公告)号：US20120229703A1

公开(公告)日：2012-09-13

申请号：US13499545

申请日：2010-10-01

Applicant: Gabriele Sartori ,  Subir Ghosh ,  Nikolay Kovach

Inventor： Gabriele Sartori ,  Subir Ghosh ,  Nikolay Kovach

IPC: H04N5/04

CPC classification number: G09G5/12 ,  G09G2370/022 ,  H04N7/083

Abstract: Thin-client terminal systems allow computer systems to be shared by multiple computer users. With modern technology, the cost of implementing a thin-client terminal system can be very low. To improve thin-client terminal systems, a thin-client terminal system accepts user input data in a first serial interface format and transcodes the user input data into a second serial interface format for transmission to a server.

Abstract translation: 瘦客户机终端系统允许计算机系统由多个计算机用户共享。 利用现代技术，实现瘦客户端终端系统的成本可能非常低。 为了改进瘦客户机终端系统，瘦客户机终端系统以第一串行接口格式接受用户输入数据，并将用户输入数据转码为第二串行接口格式以传输到服务器。