公开(公告)号：US4812688A

公开(公告)日：1989-03-14

申请号：US139551

申请日：1987-12-30

申请人： Albert M. Chu ,  William R. Griffin

发明人： Albert M. Chu ,  William R. Griffin

IPC分类号： H03H11/26 ,  H01L27/092 ,  H03K5/00 ,  H03K5/13 ,  H03K5/04 ,  H03K3/017 ,  H03K17/284 ,  H03K17/687

CPC分类号： H03K5/133 ,  H01L27/092 ,  H03K2005/00195 ,  H03K2005/00215

摘要： A signal delay circuit is provided which includes first and second circuits arranged parallel to each other, the first circuit having serially connected first and second transistors and the second circuit having a third transistor, and a fourth transistor connected from the common point between the first and second transistors to the second circuit, a signal is applied to one end of the parallelly arranged first and second circuits while the first, second and fourth transistors are turned on with the third transistor being turned off.

公开(公告)号：US4591993A

公开(公告)日：1986-05-27

申请号：US554148

申请日：1983-11-21

申请人： William R. Griffin ,  Lawrence G. Heller

发明人： William R. Griffin ,  Lawrence G. Heller

IPC分类号： H01L21/8238 ,  H01L21/82 ,  H01L27/092 ,  H01L27/112 ,  H01L27/118 ,  H03K19/0948 ,  H03K19/173 ,  H03K19/094

CPC分类号： H03K19/0948 ,  H01L27/112

摘要： A methodology is provided for reducing an arbitrary Boolean logic expression to static CMOS circuits by the use of a general matrix of P channel devices and N channel devices which are interconnected in accordance with the terms of Boolean logic expressions derived from a truth table. More specifically, from a Boolean expression a sum-of-products expression giving the 1 binary data outputs of a truth table having a 0 input is found. This is accomplished by complementing, or barring, the literals which are a binary 1 when the output is 1 and leaving true or unbarred the literals that are a binary 0. Then each input of a given product term is applied to the control gate of a P channel device, which devices are connected in series with one end tied to a source of potential and the other end of the series circuit connected to an output terminal. Each product term is arranged in parallel with other P channel device series circuits to form one half of a complete logic matrix. Similarly, for the other half of the matrix, a sum-of-products expression giving the binary 0 outputs of a truth table having a binary 1 for an input is found. Each input of a given product term is applied to the control gate of an N channel device, which devices are connected in series with one end tied to a potential reference point, such as ground, and the other end of the series circuit is connected to the output terminal. Each product term is arranged in parallel with other N channel device series circuits.

摘要翻译： 提供了一种通过使用根据从真值表导出的布尔逻辑表达式的术语互连的P通道器件和N沟道器件的通用矩阵来将静态CMOS电路的任意布尔逻辑表达式减少的方法。 更具体地，从布尔表达式中，找到给出具有0输入的真值表的1个二进制数据输出的乘积和表达式表达式。 这是通过补充或限制当输出为1时为二进制1的文字，并将真实的或未被标记为二进制0的文字来实现的。然后，将给定产品项的每个输入应用于 P通道器件，这些器件串联连接到电位源的一端，串联电路的另一端连接到输出端子。 每个产品术语与其他P通道器件串联电路并联布置，形成完整逻辑矩阵的一半。 类似地，对于矩阵的另一半，找到给出用于输入的具有二进制1的真值表的二进制0输出的乘积和表达式。 给定产品项的每个输入被施加到N沟道器件的控制栅极，这些器件与连接到诸如地的参考点的一端串联连接，串联电路的另一端连接到 输出端子。 每个产品术语与其他N通道器件串联电路并联布置。