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11.发明申请公开(公告)号：US20120162184A1
公开(公告)日：2012-06-28
申请号：US13209521
申请日：2011-08-15
Applicant: Young-Su KIM , Jae-Hoon LEE , Chang-Ho LEE , Yu-Han BAE
Inventor： Young-Su KIM , Jae-Hoon LEE , Chang-Ho LEE , Yu-Han BAE
IPC: G09G5/00
CPC classification number: G09G3/3655 , G09G2320/0214
Abstract: A method of driving a display panel includes applying a common voltage to the display panel, sensing a frequency of the display panel to generate a frequency signal, adjusting a gain of an operational amplifier based on the frequency signal, receiving a feedback common voltage from the display panel, and compensating the common voltage using an input resistor, the operational amplifier and a feedback resistor based on the feedback common voltage to apply the compensated common voltage to the display panel. The operational amplifier includes an inverting input terminal connected to the input resistor, a non-inverting input terminal to which a reference common voltage is applied and an output terminal. The feedback resistor is between the inverting input terminal and the output terminal.
Abstract translation: 驱动显示面板的方法包括向显示面板施加公共电压，感测显示面板的频率以产生频率信号，基于频率信号调整运算放大器的增益，从所述频率信号接收反馈公共电压 显示面板，并使用输入电阻器，运算放大器和基于反馈公共电压的反馈电阻器补偿公共电压，以将补偿的公共电压施加到显示面板。 运算放大器包括连接到输入电阻器的反相输入端子，施加参考公共电压的非反相输入端子和输出端子。 反馈电阻位于反相输入端和输出端之间。
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公开(公告)号：US20110273416A1
公开(公告)日：2011-11-10
申请号：US12885785
申请日：2010-09-20
Applicant: Yu-Han Bae , Young-Su Kim , Jae-Hoon Lee
Inventor： Yu-Han Bae , Young-Su Kim , Jae-Hoon Lee
CPC classification number: H02M3/07 , G09G3/3648 , G09G3/3677 , G09G2230/00 , G09G2300/0408 , G09G2310/0286 , G11C5/145 , G11C19/28 , H02M2003/072
Abstract: A voltage generating circuit includes a first charge pumping part and a second charge pumping part. The first charge pumping part pumps a switching voltage, in response to a reference voltage, to output a first voltage. The second charge pumping part pumps the switching voltage, in response to the first voltage, to output a second voltage that is lower than the first voltage that is varied in accordance with time.
Abstract translation: 电压产生电路包括第一电荷泵送部分和第二电荷泵送部分。 第一电荷泵送部分响应于参考电压泵送开关电压以输出第一电压。 第二电荷泵送部分响应于第一电压泵送开关电压，以输出低于根据时间变化的第一电压的第二电压。
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公开(公告)号：US09672782B2
公开(公告)日：2017-06-06
申请号：US12949931
申请日：2010-11-19
Applicant: Jae-Hoon Lee , Seung-Hwan Moon , Yong-Soon Lee , Young-Su Kim , Chang-Ho Lee , Whee-Won Lee , Jun-Yong Song , Yu-Han Bae
Inventor： Jae-Hoon Lee , Seung-Hwan Moon , Yong-Soon Lee , Young-Su Kim , Chang-Ho Lee , Whee-Won Lee , Jun-Yong Song , Yu-Han Bae
CPC classification number: G09G3/3677 , G09G2300/0408 , G09G2310/0267 , G09G2310/0286 , G09G2330/021 , G11C19/28
Abstract: A display panel includes an amorphous silicon gate driver in which a lower voltage than the gate-off voltage output from the gate driver is applied to an adjacent stage as a low voltage transmission signal.
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公开(公告)号：US09047841B2
公开(公告)日：2015-06-02
申请号：US13104087
申请日：2011-05-10
Applicant: JunYong Song , Jaehoon Lee , Yu-Han Bae
Inventor： JunYong Song , Jaehoon Lee , Yu-Han Bae
CPC classification number: G09G3/3677 , G09G3/003 , G09G2310/08
Abstract: A display apparatus includes: a display panel which displays an image based on a display mode; a data driver which provides data signals to the display panel; a gate driver which starts an operation thereof in response to a start signal, and comprises stages and at least two dummy stages, where the stages sequentially provides gate signals to the display panel; and a timing controller which selects a signal from the start signal and a reset signal based on the display mode and outputs the selected signal selected to the at least two dummy stages, where each stage receives a clock signal, a previous carry signal from a previous stage, a first subsequent carry signal from a first subsequent stage and a second subsequent carry signal from a second subsequent stage, and outputs a corresponding gate signal of the gate signals and a carry signal.
Abstract translation: 显示装置包括：基于显示模式显示图像的显示面板; 数据驱动器，其向显示面板提供数据信号; 门驱动器，其响应于起始信号开始其操作，并且包括级和至少两个虚级，其中级顺序地向显示面板提供门信号; 以及定时控制器，其基于所述显示模式选择来自所述起始信号的信号和复位信号，并且将选择的所选择的信号输出到所述至少两个虚拟级，其中每个级接收时钟信号，来自前一个的先前进位信号 来自第一后续级的第一后续进位信号和来自第二后续级的第二后续进位信号，并输出门信号和进位信号的对应门信号。
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公开(公告)号：US20120139883A1
公开(公告)日：2012-06-07
申请号：US13292661
申请日：2011-11-09
Applicant: Jae-Hoon LEE , Young-Su KIM , Whee-Won LEE , Jun-Yong SONG , Yu-Han BAE , You-Mee HYUN
Inventor： Jae-Hoon LEE , Young-Su KIM , Whee-Won LEE , Jun-Yong SONG , Yu-Han BAE , You-Mee HYUN
CPC classification number: G09G3/3611 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2320/041 , G11C19/28
Abstract: A gate drive circuit includes a shift register in which plural stages are cascade-connected to each other. In an n-th stage, a pull-up part outputs a high voltage of a clock signal to an output node as a high voltage of an n-th gate signal in response to a high voltage on a first node. A pull-down part pulls the high voltage of the n-th gate signal down to a first low voltage in response to an (n+1)th carry signal. A discharging part discharges the first node to a second low voltage level lower than the first low voltage level in response to the (n+1)th carry signal. A carry part outputs the high voltage of the clock signal as an n-th carry signal (mirroring the n-th gate signal) in response to a high voltage on the first node.
Abstract translation: 栅极驱动电路包括其中多级级联连接的移位寄存器。 在第n级中，上拉部分响应于第一节点上的高电压，将时钟信号的高电压输出到输出节点作为第n栅极信号的高电压。 下拉部分响应于第（n + 1）个进位信号将第n个门信号的高电压降低到第一低电压。 放电部分响应于第（n + 1）个进位信号，将第一节点放电到比第一低电压电平低的第二低电压电平。 进位部分响应于第一节点上的高电压，输出时钟信号的高电压作为第n个进位信号（反映第n个门信号）。
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Patent Agency Ranking
公开(公告)号：US08054272B2
公开(公告)日：2011-11-08
申请号：US12412070
申请日：2009-03-26
Applicant: Chang-Soo Lee , Yu-Han Bae
Inventor： Chang-Soo Lee , Yu-Han Bae
IPC: G09G3/36
CPC classification number: G09G3/3655 , G02F1/13394 , G02F1/1345 , G02F2201/121 , G02F2202/16 , G09G2300/0426 , G09G2300/043 , G09G2320/0219 , G09G2320/0223
Abstract: A display apparatus includes a gate driver, a data driver, a display panel, a power supply and a common voltage line. The gate driver outputs a gate signal, and the data driver outputs a data signal. The display panel includes a display area displaying images in response to the gate signal and the data signal, and a peripheral area surrounding the display area. The power supply generates a common voltage and supplies the common voltage to the display panel. The common voltage line is disposed in the peripheral area surrounding the display area. and the common voltage line has two ends adjacent to the power supply. One of the two ends, which is disposed farther away from the gate driver, is connected to the power supply to receive the common voltage. Accordingly, the common voltage is differentially applied according to a length of the common voltage line.
Abstract translation: 显示装置包括栅极驱动器，数据驱动器，显示面板，电源和公共电压线。 栅极驱动器输出栅极信号，数据驱动器输出数据信号。 显示面板包括响应于门信号和数据信号显示图像的显示区域和围绕显示区域的外围区域。 电源产生公共电压，并将公共电压提供给显示面板。 公共电压线设置在显示区域周围的周边区域中。 并且公共电压线具有与电源相邻的两端。 远离栅极驱动器设置的两端之一连接到电源以接收公共电压。 因此，公共电压根据公共电压线的长度差分施加。
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公开(公告)号：US20100265238A1
公开(公告)日：2010-10-21
申请号：US12762470
申请日：2010-04-19
Applicant: Jae-Hoon LEE , Yong-Soon LEE , Young-Su KIM , Yu-Han BAE
Inventor： Jae-Hoon LEE , Yong-Soon LEE , Young-Su KIM , Yu-Han BAE
CPC classification number: G09G3/3614 , G09G3/3607 , G09G2300/0426 , G09G2320/0209
Abstract: A display device includes a display panel, a data driving part and a gate driving part. The display panel includes a first pixel row. The first pixel row includes a first pixel connected to an (n+1)-th gate line and an (m+1)-th data line (where ‘n’ and ‘m’ are natural numbers), and a second pixel connected to an n-th gate line and an (m+2)-th data line. The data driving part applies a data voltage having a first polarity with respect to a reference voltage to the (m+1)-th data line, and applies a data voltage having a second polarity with respect to the reference voltage to the (m+2)-th data line. The gate driving part sequentially applies a gate signal to the n-th gate line and the (n+1)-th gate line.
Abstract translation: 显示装置包括显示面板，数据驱动部和门驱动部。 显示面板包括第一像素行。 第一像素行包括连接到第（n + 1）栅极线和第（m + 1）数据线（其中'n'和'm'是自然数）的第一像素，并且第二像素连接 到第n个栅极线和第（m + 2）个数据线。 数据驱动部分对第（m + 1）数据线施加相对于参考电压具有第一极性的数据电压，并将相对于参考电压具有第二极性的数据电压施加到第（m + 2）数据线。 栅极驱动部分顺序地对第n条栅极线和第（n + 1）栅极线施加栅极信号。
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公开(公告)号：US20090273552A1
公开(公告)日：2009-11-05
申请号：US12112918
申请日：2008-04-30
Applicant: In-Jae Hwang , Sang-Moon Moh , Yu-Han Bae
Inventor： In-Jae Hwang , Sang-Moon Moh , Yu-Han Bae
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G2330/021
Abstract: A display apparatus includes a panel part, a data driver, and a gate driver. The panel part includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels each of which is connected to one gate line of the gate lines and one data line of the data lines. The data driver receives image data and outputs a data signal to the data lines. The gate driver part is disposed on the panel part and applies gate signals to the gate lines. Periods of clock signals controlling the level of the gate signals are different from that of the gate signals. Thus, power consumption of the display apparatus is substantially effectively reduced.
Abstract translation: 显示装置包括面板部分，数据驱动器和门驱动器。 面板部分包括多条栅极线，多条数据线和多个像素，每个像素连接到栅极线的一条栅极线和数据线的一条数据线。 数据驱动器接收图像数据并将数据信号输出到数据线。 栅极驱动器部分设置在面板部分上，并将栅极信号施加到栅极线。 控制门信号电平的时钟信号周期与门信号不同。 因此，显着地降低了显示装置的功耗。
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公开(公告)号：US08957882B2
公开(公告)日：2015-02-17
申请号：US13292661
申请日：2011-11-09
Applicant: Jae-Hoon Lee , Young-Su Kim , Whee-Won Lee , Jun-Yong Song , Yu-Han Bae , You-Mee Hyun
Inventor： Jae-Hoon Lee , Young-Su Kim , Whee-Won Lee , Jun-Yong Song , Yu-Han Bae , You-Mee Hyun
CPC classification number: G09G3/3611 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2320/041 , G11C19/28
Abstract: A gate drive circuit includes a shift register in which plural stages are cascade-connected to each other. In an n-th stage, a pull-up part outputs a high voltage of a clock signal to an output node as a high voltage of an n-th gate signal in response to a high voltage on a first node. A pull-down part pulls the high voltage of the n-th gate signal down to a first low voltage in response to an (n+1)th carry signal. A discharging part discharges the first node to a second low voltage level lower than the first low voltage level in response to the (n+1)th carry signal. A carry part outputs the high voltage of the clock signal as an n-th carry signal (mirroring the n-th gate signal) in response to a high voltage on the first node.
Abstract translation: 栅极驱动电路包括其中多级级联连接的移位寄存器。 在第n级中，上拉部分响应于第一节点上的高电压，将时钟信号的高电压输出到输出节点作为第n栅极信号的高电压。 下拉部分响应于第（n + 1）个进位信号将第n个门信号的高电压降低到第一低电压。 放电部分响应于第（n + 1）个进位信号，将第一节点放电到比第一低电压电平低的第二低电压电平。 进位部分响应于第一节点上的高电压，输出时钟信号的高电压作为第n个进位信号（反映第n个门信号）。
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20.发明授权Method of driving display panel and display apparatus for performing the same 失效驱动显示面板的方法和执行该显示面板的显示装置公开(公告)号：US08773339B2
公开(公告)日：2014-07-08
申请号：US13209521
申请日：2011-08-15
Applicant: Young-Su Kim , Jae-Hoon Lee , Chang-Ho Lee , Yu-Han Bae
Inventor： Young-Su Kim , Jae-Hoon Lee , Chang-Ho Lee , Yu-Han Bae
IPC: G09G5/00
CPC classification number: G09G3/3655 , G09G2320/0214
Abstract: A method of driving a display panel includes applying a common voltage to the display panel, sensing a frequency of the display panel to generate a frequency signal, adjusting a gain of an operational amplifier based on the frequency signal, receiving a feedback common voltage from the display panel, and compensating the common voltage using an input resistor, the operational amplifier and a feedback resistor based on the feedback common voltage to apply the compensated common voltage to the display panel. The operational amplifier includes an inverting input terminal connected to the input resistor, a non-inverting input terminal to which a reference common voltage is applied and an output terminal. The feedback resistor is between the inverting input terminal and the output terminal.
Abstract translation: 驱动显示面板的方法包括向显示面板施加公共电压，感测显示面板的频率以产生频率信号，基于频率信号调整运算放大器的增益，从所述频率信号接收反馈公共电压 显示面板，并使用输入电阻器，运算放大器和基于反馈公共电压的反馈电阻器补偿公共电压，以将补偿的公共电压施加到显示面板。 运算放大器包括连接到输入电阻器的反相输入端子，施加参考公共电压的非反相输入端子和输出端子。 反馈电阻位于反相输入端和输出端之间。
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