PWM CONTROL SCHEME FOR PROVIDING MINIMUM ON TIME

    公开(公告)号:US20190020274A1

    公开(公告)日:2019-01-17

    申请号:US16030800

    申请日:2018-07-09

    IPC分类号: H02M3/07 H02M3/157

    摘要: According to certain aspects, the present embodiments are based on an improved switched-capacitor (SC) converter topology that typically does not include an inductor. In particular, the topology includes a ladder SC circuit configured as a cap divider. The cap divider can be used to provide an unregulated output voltage Vout that is a certain fraction (e.g. 2) of input voltage Vin, such as Vin/2 (i.e., duty cycle≈50%). In some embodiments of a PWM control scheme for this topology, the PWM OFF pulse is free running, determined by the logic combination of timer and VOUT comparator. The PWM OFF pulse width is measured and used as the reference for a minimum PWM ON timer. The PWM ON pulse is therefore forced to be at least a minimum width that is proportional to the PWM OFF pulse. A UVOV protection window can be added to ignore the minimum PWM ON timer during a load transient.

    Converter
    3.
    发明授权

    公开(公告)号:US10003257B2

    公开(公告)日:2018-06-19

    申请号:US15116725

    申请日:2015-02-06

    IPC分类号: H02M3/07

    CPC分类号: H02M3/07 H02M2003/072

    摘要: A DC to DC converter for converting voltage between two voltage levels is described. The converter comprises a plurality of capacitors and switch units and is controllable between a first and second commutation state. In the first commutation state, the converter is configured for connection to higher voltage terminals and the capacitors are connected in series. In the second commutation state, the converter is configured for connection to lower voltage terminals, and the capacitors are connected to form at least two branches connected in parallel, the branches comprising a series connection of at least two capacitors. In some embodiments, one or more intermediate commutation states may also be provided.

    Step-down circuit
    6.
    发明授权

    公开(公告)号:US09735682B1

    公开(公告)日:2017-08-15

    申请号:US15250816

    申请日:2016-08-29

    发明人: Motoki Tamura

    IPC分类号: H02M3/07 H02M3/158

    摘要: A step-down circuit includes a first transistor of N-type having a channel between an input terminal and a first node, and a gate to which a reference voltage that is lower than a peak value of an AC voltage applied to the input terminal is applied, a second transistor of P-type having a channel between the input terminal and a second node, and a gate to which the reference voltage is applied, a third transistor of N-type having a channel between the first node and an output terminal, and a gate to which the AC voltage is applied, a fourth transistor of P-type having a channel between the second node and the output terminal, and a gate to which the AC voltage is applied, a first capacitor connected between the first node and the second node, and a second capacitor connected between the output terminal and a reference potential terminal.

    Multi-level switching regulator circuits and methods with finite state machine control
    7.
    发明授权
    Multi-level switching regulator circuits and methods with finite state machine control 有权
    多级开关稳压器电路及方法采用有限状态机控制

    公开(公告)号:US09595869B2

    公开(公告)日:2017-03-14

    申请号:US14634412

    申请日:2015-02-27

    摘要: The present disclosure includes multi-level switching regulator circuits and methods with finite state machine control. In one embodiment, a circuit comprises a switching regulator and a finite state machine. The switching regulator comprises high side and low side switches, and at least one capacitor. A finite state machine receiving a switching signal and a duty cycle signal to generate switch control signals to the switches. The switches are turned on and off under control of the finite state machine in response to transitions of the switching signal and the duty cycle signal. The switching signal may be generated from an envelope tracking signal, and the switching regulator may be part of an envelope tracking system.

    摘要翻译: 本公开包括具有有限状态机控制的多电平开关调节器电路和方法。 在一个实施例中,电路包括开关调节器和有限状态机。 开关调节器包括高侧和低侧开关以及​​至少一个电容器。 接收切换信号的有限状态机和占空比信号,以向开关产生开关控制信号。 响应于开关信号和占空比信号的转变,开关在有限状态机的控制下被接通和断开。 开关信号可以从包络跟踪信号产生,并且开关调节器可以是包络跟踪系统的一部分。

    SYSTEM AND METHOD FOR REDUCING POWER LOSS IN SWITCHED-CAPACITOR POWER CONVERTERS
    8.
    发明申请
    SYSTEM AND METHOD FOR REDUCING POWER LOSS IN SWITCHED-CAPACITOR POWER CONVERTERS 有权
    用于降低开关电源功率转换器的功率损耗的系统和方法

    公开(公告)号:US20160352218A1

    公开(公告)日:2016-12-01

    申请号:US15116780

    申请日:2015-02-04

    IPC分类号: H02M3/07 H02M1/08

    摘要: A system for reducing power loss in a switched-capacitor converter includes a first and second switched capacitor sub-converter each having a flying capacitor and a first, second, third, and fourth switching device. Each switching device is controlled by one of a first, second, third, and fourth clock signal. The first, second, third and fourth clock signals of the second switched capacitor sub-converter are inverted such that the first switched capacitor sub-converter operates during a first phase and the second switched capacitor converter operates during a second phase that is 1800 degrees out of phase from the first phase. The system also includes a resonant charge sharing portion for coupling a bottom-plate parasitic capacitance of the first switched capacitor sub-converter to a bottom-plate parasitic capacitance of the second switched capacitor converter.

    摘要翻译: 一种用于降低开关电容器转换器中的功率损耗的系统包括具有飞跨电容器和第一,第二,第三和第四开关装置的第一和第二开关电容器子转换器。 每个开关装置由第一,第二,第三和第四时钟信号之一控制。 第二开关电容器子转换器的第一,第二,第三和第四时钟信号被反相,使得第一开关电容器子转换器在第一阶段期间操作,并且第二开关电容器转换器在1800度的第二相位期间操作 的阶段从第一阶段。 该系统还包括谐振电荷共享部分,用于将第一开关电容器子转换器的底板寄生电容耦合到第二开关电容器转换器的底板寄生电容。

    CONVERTER
    9.
    发明申请
    CONVERTER 有权
    转换器

    公开(公告)号:US20160344286A1

    公开(公告)日:2016-11-24

    申请号:US15116725

    申请日:2015-02-06

    IPC分类号: H02M3/07

    CPC分类号: H02M3/07 H02M2003/072

    摘要: A DC to DC converter for converting voltage between two voltage levels is described. The converter comprises a plurality of capacitors and switch units and is controllable between a first and second commutation state. In the first commutation state, the converter is configured for connection to higher voltage terminals and the capacitors are connected in series. In the second commutation state, the converter is configured for connection to lower voltage terminals, and the capacitors are connected to form at least two branches connected in parallel, the branches comprising a series connection of at least two capacitors. In some embodiments, one or more intermediate commutation states may also be provided.

    摘要翻译: 描述用于转换两个电压电平之间的电压的DC-DC转换器。 转换器包括多个电容器和开关单元,并且可在第一和第二换向状态之间控制。 在第一换向状态下,转换器配置为连接到较高电压端子,电容器串联连接。 在第二换向状态下,转换器被配置为连接到较低电压端子,并且电容器被连接以形成并联连接的至少两个分支,该分支包括至少两个电容器的串联连接。 在一些实施例中,还可以提供一个或多个中间换向状态。

    Power converter
    10.
    发明授权
    Power converter 有权
    电源转换器

    公开(公告)号:US09413230B2

    公开(公告)日:2016-08-09

    申请号:US14606517

    申请日:2015-01-27

    申请人: DENSO CORPORATION

    发明人: Kazuhiro Umetani

    摘要: In a power converter, at least two main current paths each including an inductor and a transistor are connected between input terminals, and at least two storage circuits each including capacitors are correspondingly connected to branch nodes of the main current paths. Diodes are connected between the storage circuits. The transistors of the main current paths are interleaved. When one of the transistors is turned off, a current flowing in the corresponding inductor flows into the corresponding storage circuit to turn on the diodes and to charge the capacitors of the corresponding storage circuit. When another one of the transistors is turned off, a current flowing in the corresponding inductor flows into the corresponding storage circuit to turn on the diodes and charge the capacitors of the corresponding storage circuit.

    摘要翻译: 在功率转换器中,每个包括电感器和晶体管的至少两个主电流路径连接在输入端子之间,并且每个包括电容器的至少两个存储电路相应地连接到主电流路径的分支节点。 二极管连接在存储电路之间。 主电流路径的晶体管是交错的。 当晶体管中的一个截止时,流过对应的电感器的电流流入对应的存储电路,以接通二极管并对相应的存储电路进行充电。 当另一个晶体管截止时,流过对应的电感器的电流流入对应的存储电路,以接通二极管并对相应的存储电路进行充电。