摘要:
An input buffer for a high-voltage signal application is provided. The input buffer uses a clamper and an inverter to clamp the output voltage in a proper range even if the input voltage is too high or too low. The proper range of the output voltage is controlled by a voltage source and the ground, so that an electrical device can be triggered safely by the output voltage.
摘要:
An injection locked frequency divider includes a signal injection unit, a Hartley voltage controlled oscillator and a biasing unit. The signal injection unit and the biasing unit output an injection signal to the Hartley voltage controlled oscillator to bias the Hartley voltage controlled oscillator. The Hartley voltage controlled oscillator, which includes a first transistor, a second transistor and a LC tank, receives the injection signal and outputs a differential output signal through a first output terminal and a second output terminal. First terminals of the first and second transistors are respectively coupled to the first and second output terminals, and second terminals of the first and second transistors are coupled to a first node. The LC tank decides a resonant frequency of the Hartley voltage controlled oscillator and serves as a positive feedback circuit for the first and second transistors.
摘要:
A multi-phase voltage-control oscillator including a first voltage-control oscillator circuit and a second voltage-control oscillator circuit is provided. The first voltage-control oscillator circuit includes a first LC tank and a first inductor assembly unit. The second voltage-control oscillator circuit includes a second LC tank and a second inductor assembly unit. A mutual inductance effect is generated between the inductors of the first voltage-control oscillator and the inductors of the second voltage-control oscillator.
摘要:
An injection-locked frequency divider includes a ring oscillator, a signal injection circuit, a first adjustable load circuit and a second adjustable load circuit. The ring oscillator generates an oscillation signal according to a differential signal outputted by the signal injection circuit. According to an adjustable voltage, the first and second adjustable load circuits can respectively change equivalent impedances of the first adjustable load circuit and the second adjustable load circuit so that a free-running frequency of the oscillation signal of the ring oscillator is adjusted and an injection-locked frequency range of the injection-locked frequency divider is expanded.
摘要:
An injection-locked frequency divider is provided. The injection-locked frequency divider includes a variable reactance unit, a signal injection unit, a first switch, a second switch, a first transformer, and a second transformer. The variable reactance unit, the first switch, the second switch, the first transformer, and the second transformer form a transformer-based LC-tank oscillator. The signal injection unit receives an injection signal. When the injection-locked frequency divider is in a locked state, the transformer-based LC-tank oscillator outputs a frequency division signal. Employing the feedback action of the first transformer and the second transformer, the present invention not only has a wide locking range but also promotes the realization of the low operating voltage.
摘要:
A frequency synthesizer of a transceiver for generating a crystal oscillation frequency and a carry frequency having been done a process of frequency offset cancellation with that of another transceiver. The frequency offset cancellation of the frequency synthesizer is done in accordance with a wireless signal which is transmitted from another transceiver received. The frequency synthesizer has a first sigma-delta modulator receiving a signal transmitted by a transceiver at far area responding thereafter a frequency divisor value in accordance with the channel information of the received signal and a frequency offset between two.
摘要:
A frequency synthesizer of a transceiver for generating a crystal oscillation frequency and a carry frequency having been done a process of frequency offset cancellation with that of another transceiver. The frequency offset cancellation of the frequency synthesizer is done in accordance with a wireless signal which is transmitted from another transceiver received. The frequency synthesizer has a first sigma-delta modulator receiving a signal transmitted by a transceiver at far area responding thereafter a frequency divisor value in accordance with the channel information of the received signal and a frequency offset between two.
摘要:
The present invention discloses a low power consumption frequency divider circuit. It mainly comprises a signal source; a signal injection circuit; and an oscillator circuit. The low-power consumption frequency divider circuit according to the present invention mainly uses the configuration of current reused circuit to form the common current path for reducing the power loss in the disclosed frequency divider circuit.