-
公开(公告)号：US20140198138A1
公开(公告)日：2014-07-17
申请号：US14155297
申请日：2014-01-14
Applicant: Apple Inc.
Inventor： Prasanna Nambi , Jason N. Gomez , Fenghua Zheng , Paolo Sacchetto , Sandro H. Pintz , Taesung Kim , Christopher P. Tann , Marc Albrecht , David W. Lum
IPC: G09G3/36
CPC classification number: G09G3/3618 , G06T1/20 , G06T2210/52 , G09G3/36 , G09G3/3611 , G09G3/3648 , G09G3/3655 , G09G3/3696 , G09G2310/08 , G09G2320/0626 , G09G2330/02 , G09G2330/021 , G09G2340/0435 , G09G2360/18 , G09G2370/08
Abstract: The disclosure describes procedures for dynamically employing a variable refresh rate at an LCD display of a consumer electronic device, such as a laptop computer, a tablet computer, a mobile phone, or a music player device. In some configurations, the consumer electronic device can include a host system portion, having one or more processors and a display system portion, having a timing controller, a buffer circuit, a display driver, and a display panel. The display system can receive image data and image control data from a GPU of the host system, evaluate the received image control data to determine a reduced refresh rate (RRR) for employing at the display panel, and then transition to the RRR, whenever practicable, to conserve power. In some scenarios, the transition to the RRR can be a transition from a LRR of 50 hertz or above to a RRR of 40 hertz or below.
Abstract translation: 本公开描述了在诸如膝上型计算机，平板计算机，移动电话或音乐播放器设备的消费电子设备的LCD显示器上动态地采用可变刷新率的过程。 在一些配置中，消费电子设备可以包括具有一个或多个处理器的主机系统部分和具有定时控制器，缓冲电路，显示驱动器和显示面板的显示系统部分。 显示系统可以从主机系统的GPU接收图像数据和图像控制数据，评估所接收的图像控制数据，以确定在显示面板上使用的刷新率降低（RRR），然后在切实可行的情况下转换到RRR ，以节省权力。 在某些情况下，过渡到RRR可以是从50赫兹或更高的LRR到40赫兹或更低的RRR的转换。
-
公开(公告)号：US11361729B2
公开(公告)日：2022-06-14
申请号：US15861215
申请日：2018-01-03
Applicant: Apple Inc.
Inventor： Mahesh B. Chappalli , Christopher P. Tann , Peter F. Holland , Guy Côté , Stephan Lachowsky
Abstract: An electronic display pipeline may process image data for display on an electronic display. The electronic display pipeline may include burn-in compensation statistics collection circuitry and burn-in compensation circuitry. The burn-in compensation statistics collection circuitry may collect image statistics based at least in part on the image data. The statistics may estimate a likely amount of non-uniform aging of the sub-pixels of the electronic display. The burn-in compensation circuitry may apply a gain to sub-pixels of the image data to account for non-uniform aging of corresponding sub-pixels of the electronic display. The applied gain may be based at least in part on the image statistics collected by the burn-in compensation statistics collection circuitry.
-
公开(公告)号：US10482806B2
公开(公告)日：2019-11-19
申请号：US14635763
申请日：2015-03-02
Applicant: APPLE INC.
Inventor： Marc Albrecht , David S. Zalatimo , Christopher P. Tann , Sandro H. Pintz
IPC: G09G3/20
Abstract: Devices and methods for reducing or eliminating spatiotemporal dithering image artifacts are provided. By way of example, a method includes providing positive polarity and negative polarity data signals to a plurality of pixels of a display during a first frame period, in which the first frame period corresponds a first spatiotemporal rotation phase. The method includes providing the positive polarity signals and the negative polarity signals to the plurality of pixels of the display during a second frame period, in which the second frame period corresponds a second spatiotemporal rotation phase. A spatiotemporal rotation phase sequence provided to the display comprises the first spatiotemporal rotation phase and the second spatiotemporal rotation phase. One of the first spatiotemporal rotation phase and the second spatiotemporal rotation phase of the spatiotemporal rotation phase sequence is altered during the first frame period or the second time period.
-
公开(公告)号：US10276085B2
公开(公告)日：2019-04-30
申请号：US14973517
申请日：2015-12-17
Applicant: Apple Inc.
Inventor： Chaohao Wang , Paolo Sacchetto , Marc Albrecht , Christopher P. Tann , Shih-Chyuan Fan Jiang , Howard H. Tang , James E. C. Brown , Zhibing Ge
IPC: G09G3/20
Abstract: This application relates to systems, methods, and apparatus for compensating voltage for pixels of a display panel based on the location of the pixels within the display panel. An amount of voltage compensation is assigned to each pixel or a group of pixels within the display panel in accordance with a calibration of the display panel. During operation of the display panel, pixel data is generated for a location of the display panel, and the pixel data is modified according to the amount of voltage compensation corresponding to the location. By modifying the pixel data in this way, spatial variations in voltage across the display panel can be mitigated in order to reduce the occurrence of certain display artifacts at the display panel.
-
公开(公告)号：US10229622B2
公开(公告)日：2019-03-12
申请号：US15812868
申请日：2017-11-14
Applicant: Apple Inc.
Inventor： Christopher P. Tann , Taesung Kim , Sandro H. Pintz
Abstract: System and method for improving displayed image quality of an electronic display that displays a first image frame by applying a first voltage to a display pixel and a second image frame directly before the first image frame by applying a second voltage to the display pixel. A display pipeline is communicatively coupled to the electronic display and receives first image data corresponding with the first image frame, where the image data includes a first grayscale value corresponding with the display pixel. Additionally the display pipeline determines an inversion balancing grayscale offset based at least in part on the first grayscale value when polarity of the first voltage and polarity of the second voltage are the same and determines magnitude of the first voltage by applying the inversion balancing grayscale offset to the first grayscale value to reduce likelihood of a perceivable luminance spike when displaying the first image frame.
-
Patent Agency Ranking
公开(公告)号：US10163385B2
公开(公告)日：2018-12-25
申请号：US14855733
申请日：2015-09-16
Applicant: Apple Inc.
Inventor： Fenghua Zheng , Christopher P. Tann , David S. Zalatimo , James E. C. Brown , Sandro H. Pintz
Abstract: A display may have an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The gate driver circuitry may include gate driver integrated circuits. Each gate driver integrated circuit may have a shift register that supplies the gate line signals to the rows of pixels. The display driver circuitry supplies a clock signal to the gate driver integrated circuits. Each gate driver integrated circuit may have one or more clock trees that are selectively enable and disabled. Each gate driver integrated circuit may have a controller and a buffer that is controlled by a control signal from the controller. The buffer may be adjusted to supply or to not supply the clock signal to an associated clock tree in that gate driver integrated circuit.
-
公开(公告)号：US20180082626A1
公开(公告)日：2018-03-22
申请号：US15655591
申请日：2017-07-20
Applicant: APPLE INC.
Inventor： Marc Albrecht , Mahesh B. Chappalli , Christopher P. Tann , Jim C. Chou , Guy Cote
IPC: G09G3/20 , G09G3/36 , G09G3/3208
CPC classification number: G09G3/2055 , G09G3/2003 , G09G3/2051 , G09G3/2059 , G09G3/3208 , G09G3/3607 , G09G3/3614 , G09G2300/0452 , G09G2320/0242 , G09G2320/0257
Abstract: Devices and methods for error diffusion and spatiotemporal dithering are provided. By way of example, a method of operating a display includes receiving a pixel input, a set of pixel coordinates, and a current frame number. A kernel and a particular kernel bit of the kernel is selected from a set of kernels, based upon the pixel input, the pixel coordinates, the frame number, or any combination thereof. A dithered output is determined based at least in part upon the kernel bit. When the display is in a diamond pixel configuration, the dithered output is applied in accordance with a diamond pattern formed by red, blue, or red and blue pixel channels.
-
公开(公告)号：US09727185B2
公开(公告)日：2017-08-08
申请号：US14640958
申请日：2015-03-06
Applicant: APPLE INC.
Inventor： Chaohao Wang , Paolo Sacchetto , Sandro H. Pintz , Christopher P. Tann , Jun Jiang , Lu Zhang
CPC classification number: G06F3/044 , G06F3/0412 , G09G3/20 , G09G3/3611 , G09G5/12 , G09G2310/08
Abstract: One embodiment describes an electronic display. The electronic display includes display driver circuitry that displays at least a first image frame and a second image frame on the electronic device using a first display pixel and a second display pixel. The electronic display also includes touch sensing circuitry that detects user interaction with the electronic display. A timing controller of the electronic display determines at least a first insertion time for a first intra-frame pause for the first image frame and a second insertion time for a second intra-frame pause for the second image frame. The first and second intra-frame pauses are periods where the display driver circuitry is pauses rendering of image data to allow the touch sensing circuitry to detect user interaction. The insertion times for the first and second intra-frame pauses are varied from one another. The timing controller inserts the first intra-frame pause during rendering of the first image frame at the first insertion time and inserts the second intra-frame pause during rendering of the second image frame at the second insertion time.
-
公开(公告)号：US20160275905A1
公开(公告)日：2016-09-22
申请号：US14661723
申请日：2015-03-18
Applicant: APPLE INC.
Inventor： Paolo Sacchetto , David W. Lum , Christopher P. Tann , Guy Cote , Chaohao Wang , Sandro H. Pintz
IPC: G09G5/00
CPC classification number: G09G5/006 , G09G2330/021 , G09G2340/02 , G09G2340/0435 , G09G2350/00 , G09G2370/10
Abstract: Methods and devices employing circuitry for dynamically adjusting bandwidth control of a display interface are provided. The display interface or image content is dynamically adjusted to support both high-speed image data (e.g., 120 Hz image data) and lower-speed content (e.g., 60 Hz content). For example, in some embodiments, additional pixel pipelines and/or processing lanes may be activated during the rendering of high-speed image data, but not during the rendering of low-speed image data. Additionally or alternatively, high-speed image data, but not low-speed data, may be compressed to render high-speed content over an interface that supports only low-speed content.
Abstract translation: 提供了采用用于动态调整显示接口的带宽控制的电路的方法和设备。 显示界面或图像内容被动态地调整以支持高速图像数据（例如，120Hz图像数据）和较低速度内容（例如，60Hz内容）。 例如，在一些实施例中，在渲染高速图像数据期间可以激活附加的像素管线和/或处理通道，但是在呈现低速图像数据期间不会激活。 另外或替代地，高速图像数据而不是低速数据可以被压缩以通过仅支持低速内容的接口呈现高速内容。
-
公开(公告)号：US20160260387A1
公开(公告)日：2016-09-08
申请号：US14635763
申请日：2015-03-02
Applicant: APPLE INC.
Inventor： Marc Albrecht , David S. Zalatimo , Christopher P. Tann , Sandro H. Pintz
CPC classification number: G09G3/2044 , G09G3/2051 , G09G3/2055 , G09G2320/0271
Abstract: Devices and methods for reducing or eliminating spatiotemporal dithering image artifacts are provided. By way of example, a method includes providing positive polarity and negative polarity data signals to a plurality of pixels of a display during a first frame period, in which the first frame period corresponds a first spatiotemporal rotation phase. The method includes providing the positive polarity signals and the negative polarity signals to the plurality of pixels of the display during a second frame period, in which the second frame period corresponds a second spatiotemporal rotation phase. A spatiotemporal rotation phase sequence provided to the display comprises the first spatiotemporal rotation phase and the second spatiotemporal rotation phase. One of the first spatiotemporal rotation phase and the second spatiotemporal rotation phase of the spatiotemporal rotation phase sequence is altered during the first frame period or the second time period.
Abstract translation: 提供了用于减少或消除时空抖动图像伪影的装置和方法。 作为示例，一种方法包括在第一帧周期期间向显示器的多个像素提供正极性和负极性数据信号，其中第一帧周期对应于第一时空旋转相位。 该方法包括在第二帧周期期间向显示器的多个像素提供正极性信号和负极性信号，其中第二帧周期对应于第二时空旋转相位。 提供给显示器的时空旋转相位序列包括第一时空旋转相位和第二时空旋转相位。 时空旋转相位序列的第一个时空旋转相位和第二时空旋转相位之一在第一帧周期或第二时间段期间被改变。
-
-
-
-
-
-
-
-
-
Search Results
73
records
(took 0.021 seconds)
