System on a chip that drives display when CPUs are powered down

    公开(公告)号:US11822416B2

    公开(公告)日:2023-11-21

    申请号:US17934976

    申请日:2022-09-23

    Applicant: Apple Inc.

    CPC classification number: G06F1/3287 G06F1/3228 H04B17/318

    Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.

    Electronic display pipeline power management systems and methods

    公开(公告)号:US11614791B2

    公开(公告)日:2023-03-28

    申请号:US17111294

    申请日:2020-12-03

    Applicant: Apple Inc.

    Abstract: An electronic device may include a display panel. When content of an image frame is expected to consume relatively higher amounts of power, a controller of the electronic device may operate a switch to change a power supply of the display panel to be a power management integrated circuit of the electronic device. However, when content of an image frame is expected to consume relatively less amounts of power, the controller may operate the switch to change the power supply of the display panel to be a power supply of an electronic display, such as a power supply used to power driver circuitry of the electronic display.

    Electronic display power management systems and methods

    公开(公告)号:US11442528B2

    公开(公告)日:2022-09-13

    申请号:US17195362

    申请日:2021-03-08

    Applicant: Apple Inc.

    Abstract: An electronic device may include a display panel to display images based on corresponding image data and an image source to pre-render a flip-book including a first image frame for display at a first target presentation time and a second image frame for display at a second target presentation time. The electronic device may also include a display pipeline coupled between the display panel and the image source having image data processing circuitry to process image data for display. The electronic device may also include a controller to instruct the display pipeline to process image data, to determine a power-on time based on a target presentation time, and to instruct the display pipeline to power-gate the image data processing circuitry upon completion of the processing of image data and until the power-on time is reached.

    ELECTRONIC DISPLAY PIPELINE POWER MANAGEMENT SYSTEMS AND METHODS

    公开(公告)号:US20220083122A1

    公开(公告)日:2022-03-17

    申请号:US17111294

    申请日:2020-12-03

    Applicant: Apple Inc.

    Abstract: An electronic device may include a display panel. When content of an image frame is expected to consume relatively higher amounts of power, a controller of the electronic device may operate a switch to change a power supply of the display panel to be a power management integrated circuit of the electronic device. However, when content of an image frame is expected to consume relatively less amounts of power, the controller may operate the switch to change the power supply of the display panel to be a power supply of an electronic display, such as a power supply used to power driver circuitry of the electronic display.

    ELECTRONIC DISPLAY POWER MANAGEMENT SYSTEMS AND METHODS

    公开(公告)号:US20210191499A1

    公开(公告)日:2021-06-24

    申请号:US17195362

    申请日:2021-03-08

    Applicant: Apple Inc.

    Abstract: An electronic device may include a display panel to display images based on corresponding image data and an image source to pre-render a flip-book including a first image frame for display at a first target presentation time and a second image frame for display at a second target presentation time. The electronic device may also include a display pipeline coupled between the display panel and the image source having image data processing circuitry to process image data for display. The electronic device may also include a controller to instruct the display pipeline to process image data, to determine a power-on time based on a target presentation time, and to instruct the display pipeline to power-gate the image data processing circuitry upon completion of the processing of image data and until the power-on time is reached.

    BURN-IN STATISTICS WITH LUMINANCE BASED AGING

    公开(公告)号:US20210183333A1

    公开(公告)日:2021-06-17

    申请号:US16711319

    申请日:2019-12-11

    Applicant: Apple Inc.

    Abstract: An electronic device may include an electronic display and a display pipeline. The electronic display may include multiple pixels to display images based at least in part on pixel data. The display pipeline may receive image data and process the image data to determine the pixel data. The display pipeline may include burn-in compensation circuitry to apply gains to the image data based at least in part on burn-in statistics to generate the pixel data. The gain to be applied to the image data for a pixel of the electronic display is determined by the burn-in compensation circuitry, based at least in part on an emission duty cycle of the pixel, to compensate the image data for the pixel for burn-in related aging of the pixel.

    Multi-frame-history pixel drive compensation

    公开(公告)号:US10971079B2

    公开(公告)日:2021-04-06

    申请号:US16545975

    申请日:2019-08-20

    Applicant: Apple Inc.

    Abstract: Image data for a current image frame may be compensated for transient response variations due to changes to pixel values from one frame to another over time by performing pixel drive compensation. The pixel drive compensation may be performed using a current pixel value and a historical pixel value. The historical pixel value may be the same as a pixel value in the directly previous frame in some conditions, while in other conditions the historical pixel value may be modified from a previous image frame in light of a prior pixel value occurring before the previous image frame. In this way, drive compensation corresponding to image data of a subsequent image frame may be determined based at least in part on a multi-frame history. Even so, the memory bandwidth and/or power consumed to use a multi-frame history to determine a drive compensation may be reduced.

    ELECTRONIC DISPLAY FRAME PRE-NOTIFICATION SYSTEMS AND METHODS

    公开(公告)号:US20200082783A1

    公开(公告)日:2020-03-12

    申请号:US16128347

    申请日:2018-09-11

    Applicant: Apple Inc.

    Abstract: An electronic device may include a display panel to display an image and a display pipeline to process image data for the image. The display pipeline may include a controller to determine a first potential presentation time based on a maximum refresh rate of the display panel. The controller may also determine if a second target presentation time of a second image is equal to the first potential presentation time before a pipeline configuration time, and if the second target presentation time of the second image is equal to a second potential presentation time that occurs after the first potential presentation time and before a first pre-notification time occurring before the pipeline configuration time. The controller may output a first pre-notification signal at the first pre-notification time that instructs the display panel to pause self-refreshes until after the second image is displayed.

    ELECTRONIC DISPLAY REDUCED BLANKING DURATION SYSTEMS AND METHODS

    公开(公告)号:US20200064902A1

    公开(公告)日:2020-02-27

    申请号:US16110953

    申请日:2018-08-23

    Applicant: Apple Inc.

    Abstract: The configuration buffer may be divided into partitions that may effectively function as multiple linked configuration buffers. The linked partitions may each be associated with a portion of the display pipeline (e.g., an image process block) and may each be responsible for loading configuration entries into the programmable register(s) of a portion of the display pipeline. In this manner, the partitions may load the associated programmable register(s) of the display pipeline substantially simultaneously, reducing the time used to configure the entire display pipeline. Since configuration of the display pipeline may occur during the blanking period, a reduction in display pipeline configuration time may reduce the blanking period and increase the time for driving pixels of the display, thereby improving perceived image quality (e.g., pixel yield of the display panel).

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