公开(公告)号：US20200310812A1

公开(公告)日：2020-10-01

申请号：US16364570

申请日：2019-03-26

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Muhammad Umar FAROOQ

IPC: G06F9/38 ,  G06F9/30

Abstract: An apparatus and method are provided for making predictions for instruction flow changing instructions. The apparatus has a fetch queue that identifies a sequence of instructions to be fetched for execution by execution circuitry, and prediction circuitry for making predictions in respect of instruction flow changing instructions, and for controlling which instructions are identified in the fetch queue in dependence on the predictions. The prediction circuitry is arranged, during each prediction iteration, to make a prediction for a predict block comprising a sequence of M instruction addresses, in order to identify whether that predict block contains the instruction address for an instruction flow changing instruction that is predicted as taken. During each prediction iteration, the prediction circuitry is arranged by default to access a prediction storage in order to produce prediction information for instructions associated with a specified block of instruction addresses (including at least the predict block being considered), and to use that prediction information to make the prediction for the predict block. Buffer storage is used to retain the prediction information obtained from the prediction storage during one or more previous prediction iterations, and detection circuitry is used to detect when a current predict block being considered during a current prediction iteration comprises one or more instruction addresses for which the associated prediction information is retained in the buffer storage. In that event, the above default behaviour is not adopted, and an override condition is triggered to cause the prediction information for those one or more instruction addresses to be obtained from the buffer storage rather than from the prediction storage, giving rise to a power saving.

公开(公告)号：US20200310811A1

公开(公告)日：2020-10-01

申请号：US16364557

申请日：2019-03-26

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Muhammad Umar FAROOQ

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

Abstract: An apparatus and method are provided for making predictions for instruction flow changing instructions. The apparatus has a fetch queue that identifies a sequence of instructions to be fetched for execution by execution circuitry, and prediction circuitry for making predictions in respect of instruction flow changing instructions, and for controlling which instructions are identified in the fetch queue in dependence on the predictions. The prediction circuitry has a target prediction storage used to identify target addresses for instruction flow changing instructions that are predicted as taken. The target prediction storage comprises at least one entry that is configurable as a multi-taken entry to indicate that a source instruction flow changing instruction identified by that entry is a first instruction flow changing instruction with an associated first target address that identifies a series of instructions that is expected to exhibit static behaviour and that terminates with a second instruction flow changing instruction, where the second instruction flow changing instruction is unconditionally taken and has an associated second target address. The prediction circuitry is arranged, when making a prediction for a chosen instruction flow changing instruction that is identified by a multi-taken entry in the target prediction storage, to identify with reference to target address information stored in that multi-taken entry both the series of instructions and a target instruction at the second target address. It then causes the series of instructions and the target instruction to be identified in the fetch queue, and begins making further predictions starting from the target instruction at the second target address.

公开(公告)号：US20180095752A1

公开(公告)日：2018-04-05

申请号：US15281226

申请日：2016-09-30

Applicant: ARM LIMITED

Inventor： Vasu KUDARAVALLI ,  Matthew Paul ELWOOD ,  Adam GEORGE ,  Muhammad Umar FAROOQ ,  Michael FILIPPO

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875

CPC classification number: G06F12/0875 ,  G06F8/41 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3017 ,  G06F9/30196 ,  G06F9/3808 ,  G06F9/382 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3846 ,  G06F9/3848 ,  G06F2212/452

Abstract: An apparatus comprises processing circuitry, an instruction cache, decoding circuitry to decode program instructions fetched from the cache to generate macro-operations to be processed by the processing circuitry, and predecoding circuitry to perform a predecoding operation on a block of program instructions fetched from a data store to generate predecode information to be stored to the cache with the block of instructions. In one example the predecoding operation comprises generating information on how many macro-operations are to generated by the decoding circuitry for a group of one or more program instructions. In another example the predecoding operation comprises generating information indicating whether at least one of a given subset of program instructions within the prefetched block is a branch instruction.