公开(公告)号：US20230388651A1

公开(公告)日：2023-11-30

申请号：US18323768

申请日：2023-05-25

Applicant: Arm Limited

Inventor： Daniel Fedai LARSEN ,  Tord Kvestad ØYGARD ,  Frank Klaeboe LANGTIND ,  Andreas Due ENGH-HALSTVEDT

IPC: H04N23/73 ,  G06T5/00

CPC classification number: H04N23/73 ,  G06T5/009 ,  G06T2207/20172

Abstract: A method of processing data in a graphics processor when performing tile-based rendering in which a render output is sub-divided into a plurality of tiles for rendering. The rendering is performed as two separate processing passes: a first processing pass that sorts primitives into respective regions of the render output and a second processing pass that renders the tiles into which the render output is sub-divided for rendering. During the first processing pass, “tile elimination” data is generated indicative of which of the rendering tiles should be rendered during the second processing pass. The tile elimination data generated in the first processing pass can then be used to control the rendering of tiles during the second processing pass.

公开(公告)号：US20190079867A1

公开(公告)日：2019-03-14

申请号：US16129560

申请日：2018-09-12

Applicant: Arm Limited

Inventor： Antonio GARCÍA GUIRADO ,  Andreas Due ENGH-HALSTVEDT

IPC: G06F12/0811 ,  G06F12/128

Abstract: Cache storage comprising cache lines, each configured to store respective data entries. The cache storage is configured to store a tag in the form of: an individual tag portion which is individual to a cache line; a shareable tag portion which is shareable between cache lines; and pointer data which associates an individual tag portion with a shareable tag portion.

公开(公告)号：US20150120795A1

公开(公告)日：2015-04-30

申请号：US14584237

申请日：2014-12-29

Applicant: ARM Limited

Inventor： Jorn NYSTAD ,  Andreas Due ENGH-HALSTVEDT ,  Simon Alex CHARLES

IPC: G06F5/00

CPC classification number: G06F5/00 ,  G06F7/483 ,  G06F7/499 ,  G06F7/49963 ,  G06F9/30014 ,  G06F9/30025 ,  G06F2207/382 ,  H03M7/24

Abstract: Apparatus for processing data includes processing circuitry 16, 18, 20, 22, 24, 26 and decoder circuitry 14 for decoding program instructions. The program instructions decoded include a floating point pre-conversion instruction which performs round-to-nearest ties to even rounding upon the mantissa field of an input floating number to generate an output floating point number with the same mantissa length but with the mantissa rounded to a position corresponding to a shorter mantissa field. The output mantissa field includes a suffix of zero values concatenated the rounded value. The decoder for circuitry 14 is also responsive to an integer pre-conversion instruction to quantise and input integer value using round-to-nearest ties to even rounding to form an output integer operand with a number of significant bits matched to the mantissa size of a floating point number to which the integer is later to be converted using an integer-to-floating point conversion instruction.

Abstract translation: 用于处理数据的装置包括用于解码程序指令的处理电路16,18,20,22,24,26和解码器电路14。 所解码的程序指令包括一个浮点预转换指令，其执行圆到最近的连接，以便在输入浮点数的尾数字上偶数舍入以产生具有相同尾数长度但尾数四舍五入的输出浮点数 对应于较短的尾数字段的位置。 输出尾数字段包括将值的后缀连接在舍入值上。 用于电路14的解码器还响应于整数预转换指令，以使用向量到最近的系数对偶数四舍五入进行定量和输入整数值，以形成输出整数运算数，该输出整数操作数的数目与 使用整数到浮点转换指令后续整数的浮点数。

公开(公告)号：US20200057636A1

公开(公告)日：2020-02-20

申请号：US16661196

申请日：2019-10-23

Applicant: Arm Limited

Inventor： Andreas Due ENGH-HALSTVEDT

IPC: G06F9/30 ,  G06F12/0875 ,  G06F9/38

Abstract: Processing circuitry performs processing operations specified by program instructions. An instruction decoder decodes an atomic-add-with-carry instruction AADDC to control the processing circuitry to perform an atomic operation of an add of an addend operand value and a data value stored in a memory to generate a result value stored in the memory and a carry value indicative of whether or not the add generated a carry out. The atomic-add-with-carry instructions may be used within systems which accumulate a local sum value prior to a data value being returned into a local cache memory at which time the local sum value is added to the return data value. The atomic-add-with-carry instructions may also be used in embodiments comprising a coalescing tree of respective processing apparatus where the carry out values generated from local sums produced at each node are returned early to higher nodes within the hierarchy thereby releasing them to commence other processing.

公开(公告)号：US20180157464A1

公开(公告)日：2018-06-07

申请号：US15370660

申请日：2016-12-06

Applicant: ARM Limited

Inventor： David Raymond LUTZ ,  Neil BURGESS ,  Christopher Neal HINDS ,  Andreas Due ENGH-HALSTVEDT

IPC: G06F7/483 ,  G06F7/499

CPC classification number: G06F7/483 ,  G06F7/49915 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30036

Abstract: An apparatus and method are provided for performing arithmetic operations to accumulate floating-point numbers. The apparatus comprises execution circuitry to perform arithmetic operations, and decoder circuitry to decode a sequence of instructions in order to generate control signals to control the arithmetic operations performed by the execution circuitry. A convert and accumulate instruction is provided, and the decoder circuitry is responsive to decoding such a convert and accumulate instruction within the sequence of instructions to generate one or more control signals to control the execution circuitry. In particular, the execution circuitry is responsive to such control signals to convert at least one floating-point operand identified by the convert and accumulate instruction into a corresponding N-bit fixed-point operand having M fraction bits, where M is less than N and M is dependent on a format of the floating-point operand. In addition, the execution circuitry accumulates each corresponding N bit fixed-point operand and a P bit fixed-point operand identified by the convert and accumulate instruction in order to generate a P bit fixed-point result value, where P is greater than N and also has M fraction bits. This provides a fast and efficient mechanism for accumulating floating-point numbers in a manner that is associative, and hence enables reproducible and correct results to be generated irrespective of the order in which the floating-point numbers are accumulated.

公开(公告)号：US20160179676A1

公开(公告)日：2016-06-23

申请号：US14957117

申请日：2015-12-02

Applicant: ARM LIMITED

Inventor： Andreas Due ENGH-HALSTVEDT ,  Jørn NYSTAD

IPC: G06F12/08

Abstract: A data processing system incorporates a write-back cache and supports load-and-clean program instructions. The action of a load-and-clean program instruction is to load a data value and to mark as clean at least a target portion within a cache line of the write-back cache which is storing the data value loaded. The data values to be subject to such load-and-clean instructions may be identified by the programmer as the last use of those data values, or may be identified by a compiler as the last use of those data values. The data values may be from a stack memory region in which their pattern of access is predictable and it is known when they are no longer required. Another example of regular memory accesses where the last access can be identified is when processing streaming media data.

Abstract translation: 数据处理系统包含回写高速缓存并支持加载和清理程序指令。 加载和清理程序指令的动作是加载数据值，并标记为清除正在存储加载数据值的回写缓存的高速缓存行内的至少一个目标部分。 要受这种加载和清理指令的数据值可以由程序员识别为最后使用那些数据值，或者可以由编译器识别为这些数据值的最后使用。 数据值可以来自其存储模式是可预测的堆栈存储器区域，并且当不再需要它们时，它们是已知的。 可以识别最后一次访问的常规内存访问的另一个例子是处理流媒体数据时。

公开(公告)号：US20140225907A1

公开(公告)日：2014-08-14

申请号：US14257090

申请日：2014-04-21

Applicant: ARM Limited

Inventor： Andreas Due ENGH-HALSTVEDT ,  Jorn NYSTAD

IPC: G06F12/08 ,  G09G5/39

CPC classification number: G06F12/0802 ,  G06T1/20 ,  G09G5/39

Abstract: A graphics processing unit 2 includes a texture pipeline 6 which performs filter operations upon texture values. If the texture values are integer texture values, then they may be processed by the texture pipeline in a variable order corresponding to the order in which they are retrieved from a memory 4. If the texture values are floating point texture values, then they are processed in a fixed order in order to ensure result invariants as the filter operation is non-associative for floating point values. The filter operation is not commenced until all of the floating point texture values have been retrieved from the memory 4 and other available for processing.

Abstract translation: 图形处理单元2包括对纹理值执行滤波操作的纹理管线6。 如果纹理值是整数纹理值，则它们可以由纹理流水线以与从存储器4检索的顺序相对应的可变顺序来处理。如果纹理值是浮点纹理值，则它们被处理 以固定顺序，以确保结果不变量，因为过滤器操作对于浮点值是非关联的。 过滤器操作不会开始，直到从存储器4检索到所有浮点纹理值，并且可以处理的其他值。