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    LANE POSITION INFORMATION FOR PROCESSING OF VECTOR
    2.
    发明申请
    LANE POSITION INFORMATION FOR PROCESSING OF VECTOR 有权

    公开(公告)号：US20170139676A1

    公开(公告)日：2017-05-18

    申请号：US14939371

    申请日：2015-11-12

    申请人： ARM LIMITED

    发明人： David Raymond LUTZ ,  Neil BURGESS ,  Christopher Neal HINDS

    IPC分类号： G06F7/483 ,  G06F7/02

    CPC分类号： G06F7/483 ,  G06F7/02 ,  G06F7/499 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30192 ,  G06F9/3887 ,  G06F2207/483

    摘要： Processing circuitry performs a plurality of lanes of processing on respective data elements of at least one operand vector to generate corresponding result data elements of a result vector. The processing circuitry identifies lane position information for each lane of processing, the lane position information for a given lane identifying a relative position of the corresponding result data element to be generated by the given lane within a corresponding result data value spanning one or more result data elements of the result vector. The processing circuitry is configured to perform each lane of processing in dependence on the lane position information identified for that lane. This enables generation of results which are wider or narrower than the vector size supported in hardware.

    DYNAMIC SELECTION OF MEMORY MANAGEMENT ALGORITHM
    6.
    发明申请
    DYNAMIC SELECTION OF MEMORY MANAGEMENT ALGORITHM 有权
    动态选择存储器管理算法

    公开(公告)号：US20150355851A1

    公开(公告)日：2015-12-10

    申请号：US14300735

    申请日：2014-06-10

    申请人： ARM Limited

    发明人： Christopher Neal HINDS ,  Steven D. KRUEGER ,  Carl Wayne VINEYARD

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0617 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/467 ,  G06F13/1663

    摘要： A data processing system 2 includes a memory controller 20 which dynamically selects from a plurality of candidate management algorithms a selected management algorithm to be used for managing memory access conflicts. The memory management algorithms may include various versions of speculative memory access issue and/or memory access issue using memory locks. The dynamic selection is performed on the basis of detected state parameters of the system. These detected state parameters may include conflict level indicators, such as memory access conflict counters tracked on one or more of a global, per-process, per-region or per-thread basis.

    摘要翻译： 数据处理系统2包括存储器控制器20，其从多个候选管理算法动态地选择要用于管理存储器访问冲突的所选择的管理算法。 存储器管理算法可以包括使用存储器锁的推测存储器访问问题和/或存储器访问问题的各种版本。 基于检测到的系统状态参数进行动态选择。 这些检测到的状态参数可以包括冲突级指示符，诸如在全局，每进程，每区域或每个线程的一个或多个上跟踪的存储器访问冲突计数器。

    ANCHORED DATA ELEMENT CONVERSION
    7.
    发明申请
    ANCHORED DATA ELEMENT CONVERSION 审中-公开

    公开(公告)号：US20200249942A1

    公开(公告)日：2020-08-06

    申请号：US16424718

    申请日：2019-05-29

    申请人： Arm Limited

    发明人： David Raymond LUTZ ,  Neil BURGESS ,  Christopher Neal HINDS ,  Nigel John STEPHENS

    IPC分类号： G06F9/30 ,  H03M7/24

    摘要： An apparatus is provided, that includes an instruction decoder responsive to an anchored-data processing instruction, to generate one or more control signals. Conversion circuitry is responsive to the one or more control signals to perform a conversion from a data value to an anchored-data select value. The conversion is based on anchor metadata indicative of a given range of significance for the anchored-data select value. Output circuitry is responsive to the one or more control signals, to write the anchored-data select value to a register.

    REPETITIVE SIDE CHANNEL ATTACK COUNTERMEASURES
    8.
    发明申请
    REPETITIVE SIDE CHANNEL ATTACK COUNTERMEASURES 审中-公开

    公开(公告)号：US20200012822A1

    公开(公告)日：2020-01-09

    申请号：US16030459

    申请日：2018-07-09

    申请人： Arm Limited

    发明人： Carl Wayne VINEYARD ,  Christopher Neal HINDS ,  Adeline-Fleur FLEMING

    IPC分类号： G06F21/77 ,  G06F21/72 ,  G06F21/56

    摘要： A computing device incorporating repetitive side channel attack (SCA) countermeasures can include a timer circuit and a capacitive delay circuit that notifies of a potential repetitive-based attack by sending an activity-detected signal that can be used to initiate an appropriate countermeasure response. Additionally, or independently, a computing device incorporating repetitive SCA countermeasures can include at least one storage unit that can store an incoming input signal, at least one comparator to compare the incoming input signal with another signal and indicate a match, and a counter that increments upon the match. When the counter reaches a specified limit, a limit-exceeded signal can be sent to notify of a potential repetitive-based attack and initiate an appropriate countermeasure response.

    TRACKING EVENTS OF INTEREST TO MITIGATE ATTACKS
    9.
    发明申请
    TRACKING EVENTS OF INTEREST TO MITIGATE ATTACKS 审中-公开

    公开(公告)号：US20200012783A1

    公开(公告)日：2020-01-09

    申请号：US16409205

    申请日：2019-05-10

    申请人： Arm Limited

    发明人： Carl Wayne VINEYARD ,  Christopher Neal HINDS ,  Subbayya Chowdary YANAMADALA ,  Asaf SHEN

    IPC分类号： G06F21/55 ,  G06F21/56

    摘要： A computing device can include a comparator coupled to an I/O pin of the computing device; a storage unit coupled to the comparator; and a counter coupled to receive an output of the comparator, an output of the counter being coupled to a computation engine to provide a limit-exceeded signal to the computation engine, wherein the counter comprises a volatile counter and a nonvolatile storage, wherein the nonvolatile storage stores a bit for each top volatile count number of events identified by the volatile counter. The computing device can further include a backup power source coupled to the volatile counter; and readout circuitry and control logic coupled to the volatile counter and to the nonvolatile storage, the readout circuitry and control logic being configured to control operations of the volatile counter during an error event and determine a total number of events. The computing device can be a smart card.

    ARITHMETIC OPERATION INPUT-OUTPUT EQUALITY DETECTION
    10.
    发明申请
    ARITHMETIC OPERATION INPUT-OUTPUT EQUALITY DETECTION 审中-公开

    公开(公告)号：US20180173498A1

    公开(公告)日：2018-06-21

    申请号：US15896117

    申请日：2018-02-14

    申请人： ARM Limited

    发明人： Christopher Neal HINDS ,  David Raymond LUTZ

    IPC分类号： G06F7/485

    CPC分类号： G06F7/485 ,  G06F7/48

    摘要： Apparatus and corresponding methods are disclosed relating to circuitry to perform an arithmetic operation on one or more input operands, where the circuitry is responsive to an equivalence of a result value of the arithmetic operation with at least one of the one or more input operands, when the one or more input operands are not an identity element for the arithmetic operation, to generate a signal indicative of the equivalence. Idempotency (between at least one input operand and the result value) is thus identified.