公开(公告)号：US11954048B2

公开(公告)日：2024-04-09

申请号：US17996269

申请日：2021-04-14

Applicant: ARM LIMITED

Inventor： Jason Parker ,  Yuval Elad ,  Alexander Donald Charles Chadwick ,  Andrew Brookfield Swaine ,  Carlos Garcia-Tobin

IPC: G06F12/00 ,  G06F12/14

CPC classification number: G06F12/1483 ,  G06F12/1441 ,  G06F12/145

Abstract: An apparatus has memory management circuitry to control access to a memory system based on access control information defined in table entries of a table structure comprising at least two levels of access control table. Table accessing circuitry accesses the table structure to obtain the access control information corresponding to a target address. For a given access control table at a given level of the table structure other than a starting level, the table accessing circuitry selects a selected table entry of the given access control table corresponding to the target address, based on an offset portion of the target address. A size of the offset portion is selected based on a variable nesting control parameter specified in a table entry of a higher-level access control table at a higher level of the table structure than the given access control table.

公开(公告)号：US20240045802A1

公开(公告)日：2024-02-08

申请号：US18258849

申请日：2021-12-08

Applicant: Arm Limited

Inventor： Andrew Brookfield Swaine ,  Olof Henrik Uhrenholt

IPC: G06F12/0811 ,  G06F12/0846 ,  G06F12/1009

CPC classification number: G06F12/0811 ,  G06F12/0848 ,  G06F12/1009

Abstract: Address translation circuitry (20) converts virtual addresses into physical addresses with reference to intermediate level and final level page tables. Final level descriptors within final level page tables identify address translation data for an associated region of memory. Intermediate level descriptors within intermediate level page tables identify intermediate address translation data used to identify an associated page table at a next level of the page tables. Page table update circuitry (35) maintains state information within each final and intermediate level descriptor, and updates the state information from a clean state to a dirty state: in the final level descriptors to indicate that a modification of content of the associated memory region is permitted; in the intermediate level descriptors to indicate occurrence of an update from the clean state to the dirty state within the state information of any final level descriptors that are accessed via that intermediate level descriptor.

公开(公告)号：US11734440B2

公开(公告)日：2023-08-22

申请号：US16564282

申请日：2019-09-09

Applicant: Arm Limited

Inventor： Andrew Brookfield Swaine

IPC: G06F21/62 ,  G06F3/06

CPC classification number: G06F21/6218 ,  G06F3/0622 ,  G06F3/0659 ,  G06F3/0673

Abstract: A memory system component comprises transaction handling circuitry to receive memory access transactions. Each memory access transaction specifies at least: an issuing domain identifier which indicates an issuing security domain specified by an issuing master device for the memory access transaction, where the issuing security domain is one of a plurality of security domains; a target address; and a security check indication which indicates whether it is already known that the memory access transaction would pass a security checking procedure. The security checking procedure determines whether the memory access transaction indicating said issuing security domain is authorised to access the target address, based on control data indicative of which of the plurality of security domains are allowed to access the target address. The memory system component comprises control circuitry to determine, on the basis of the security check indication, whether the security checking procedure still needs to be performed.

公开(公告)号：US11586554B2

公开(公告)日：2023-02-21

申请号：US16937272

申请日：2020-07-23

Applicant: Arm Limited

Inventor： Olof Henrik Uhrenholt ,  Andrew Brookfield Swaine

IPC: G06F12/0895 ,  G06T1/20 ,  H03M7/30

Abstract: A data processing system is provided comprising a cache system configured to transfer data between a processor and memory system. The cache system comprises a cache. When a block of data that is stored in the memory in a compressed form is to be loaded into the cache, the block of data is stored into a group of one or more cache lines of the cache and the associated compression metadata for the compressed block of data is provided as separate side band data.

公开(公告)号：US10664400B2

公开(公告)日：2020-05-26

申请号：US15646406

申请日：2017-07-11

Applicant: ARM Limited

Inventor： Andrew Brookfield Swaine

IPC: G06F12/0846 ,  G06F12/0808 ,  G06F12/1009 ,  G06F12/1036

Abstract: An apparatus has an address translation cache with entries for storing address translation data. Partition configuration storage circuitry stores multiple sets of programmable configuration data each corresponding to a partition identifier identifying a corresponding software execution environment or master device and specifying a corresponding subset of entries of the cache. In response to a translation lookup request specifying a target address and a requesting partition identifier, control circuitry triggers a lookup operation to identify whether the target address hits or misses in the corresponding subset of entries specified by the set of partition configuration data for the requesting partition identifier.

公开(公告)号：US09507728B2

公开(公告)日：2016-11-29

申请号：US14736770

申请日：2015-06-11

Applicant: ARM LIMITED

Inventor： Andrew Brookfield Swaine ,  Gareth Evans ,  Matthew Lucien Evans

IPC: G06F13/00 ,  G06F12/10 ,  G06F13/40

CPC classification number: G06F12/1009 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/1027 ,  G06F13/405 ,  G06F2212/1016 ,  G06F2212/65

Abstract: A data processing apparatus 2 includes bridge circuitry 14, 16, 18 which serves to translate memory transactions of a first type (AXI) into memory transactions of a second type (PCI Express). The bridge circuitry includes translation circuitry 18 which maps at least some of the bits of attribute data of a memory transaction of the first type to unused bits within the significant bits of an address of the second type, which are unused to represent significant bits of the address of memory transactions of the first type.

Abstract translation: 数据处理装置2包括用于将第一类型（AXI）的存储器事务转换为第二类型（PCI Express）的存储器事务的桥接电路14,16,18。 桥接电路包括转换电路18，其将第一类型的存储器事务的属性数据的位的至少一些位映射到第二类型的地址的有效位内的未使用位，其未被用于表示第二类型的有效位 第一类内存交易的地址。

公开(公告)号：US12164436B2

公开(公告)日：2024-12-10

申请号：US17999649

申请日：2021-05-20

Applicant: Arm Limited

Inventor： Andrew Brookfield Swaine

IPC: G06F12/00 ,  G06F12/1009 ,  G06F12/1027

Abstract: Apparatus comprises address processing circuitry to detect information relating to an input memory address provided by address information tables; the address processing circuitry being configured to select an address information table at a given table level according to earlier information entry in an address information table; and the address processing circuitry being configured to select an information entry in the selected address information table according to an offset component, the offset component being defined so that contiguous instances of that portion of the input memory address indicate contiguously addressed information entries; the address processing circuitry comprising detector circuitry to detect whether indicator data is set to indicate whether a group of one or more contiguously addressed information entries in the selected address information table provide at least one base address indicating a location within a contiguously addressed region comprising multiple address information tables at a later table level.

公开(公告)号：US12164425B2

公开(公告)日：2024-12-10

申请号：US18258849

申请日：2021-12-08

Applicant: Arm Limited

Inventor： Andrew Brookfield Swaine ,  Olof Henrik Uhrenholt

IPC: G06F3/06 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/1009

Abstract: Address translation circuitry (20) converts virtual addresses into physical addresses with reference to intermediate level and final level page tables. Final level descriptors within final level page tables identify address translation data for an associated region of memory. Intermediate level descriptors within intermediate level page tables identify intermediate address translation data used to identify an associated page table at a next level of the page tables. Page table update circuitry (35) maintains state information within each final and intermediate level descriptor, and updates the state information from a clean state to a dirty state: in the final level descriptors to indicate that a modification of content of the associated memory region is permitted; in the intermediate level descriptors to indicate occurrence of an update from the clean state to the dirty state within the state information of any final level descriptors that are accessed via that intermediate level descriptor.

公开(公告)号：US12067263B2

公开(公告)日：2024-08-20

申请号：US17907205

申请日：2021-02-08

Applicant: ARM LIMITED

Inventor： Thomas Christopher Grocutt ,  Andrew Brookfield Swaine ,  Alexander Donald Charles Chadwick

IPC: G06F3/06 ,  G06F12/0891

CPC classification number: G06F3/0622 ,  G06F3/0629 ,  G06F3/0673 ,  G06F12/0891

Abstract: Apparatuses, methods and techniques for controlling memory access in a data processing system are disclosed. The operating data processing system comprises multiple subsystems, each comprising at least one processing element and at least one peripheral device. Memory transaction control circuitry receives memory transaction information of a memory transaction comprising a stream identifier indicative of the issuing peripheral device. A main control register indicates an address of a stream table having multiple entries each comprising an owning subsystem identifier. At least one subsystem control register corresponding to each subsystem of the multiple subsystems stores memory access checking configuration information. On receipt of the memory transaction information an entry of the stream table is selected in dependence on the stream identifier. At least one subsystem control register. corresponding to the subsystem identified by the owning subsystem identifier of the entry is selected.

公开(公告)号：US11934320B2

公开(公告)日：2024-03-19

申请号：US17753345

申请日：2020-08-26

Applicant: Arm Limited

Inventor： Andrew Brookfield Swaine

IPC: G06F12/1027

CPC classification number: G06F12/1027 ,  G06F2212/304

Abstract: A type of translation lookaside buffer (TLB) invalidation instruction is described which specifically targets a first type of TLB which stores combined stage-1-and-2 entries which depend on both stage 1 translation data and the stage 2 translation data, and which is configured to ignore a TLB invalidation command which invalidates based on a first set of one or more invalidation conditions including an address-based invalidation condition depending on matching of intermediate address. A second type of TLB other than the first type ignores the invalidation command triggered by the first type of TLB invalidation instruction. This approach helps to limit the performance impact of stage 2 invalidations in systems supporting a combined stage-1-and-2 TLB which cannot invalidate by intermediate address.