公开(公告)号：US12099456B2

公开(公告)日：2024-09-24

申请号：US18098360

申请日：2023-01-18

申请人： Arm Limited

发明人： Guanghui Geng ,  Andrew Brookfield Swaine

IPC分类号： G06F13/16 ,  G06F12/1027 ,  G06F12/14 ,  G06F13/22

CPC分类号： G06F13/1689 ,  G06F12/1027 ,  G06F12/1491 ,  G06F13/225

摘要： Circuitry comprises a memory to store data defining a set of one or more command queues each associated with a respective memory address space, each command queue defining successive commands for execution from a queue head to a queue tail, the commands being selected from a set of commands comprising synchronization commands and one or more other commands defining memory management operations for a given memory address space, in which completion of a synchronization command is dependent upon one or more completion criteria indicating that all commands from any of the command queues which are earlier than the synchronization command in an execution order have completed; and command processing circuitry to execute the commands; in which the command processing circuitry is configured to maintain a linked list of entries having a list order, each entry defining a respective one of the command queues, in which the command processing circuitry is configured to execute commands at the head of command queues, the command queues being defined by prevailing entries of the linked list of entries in the list order; and in which, for a current occupancy of the linked list at a given stage, the given stage being a given stage of executing commands from command queues defined by entries of the linked list, the command processing circuitry is configured to execute a synchronization command first in the list order and to detect, within that current occupancy of the linked list at the given stage, any further synchronization commands at the head of command queues which are defined by entries of the linked list later in the list order, the command processing circuitry applying, for any such further synchronization commands, the completion criteria of the synchronization command at the head of a given command queue, the given command queue being defined by an entry of the linked list earliest in the list order so as to treat any such further synchronization commands as having been completed.

公开(公告)号：US20240070071A1

公开(公告)日：2024-02-29

申请号：US18259827

申请日：2021-11-25

申请人： Arm Limited

发明人： Andrew Brookfield Swaine ,  Richard Roy Grisenthwaite

IPC分类号： G06F12/0811 ,  G06F12/0837 ,  G06F12/0875

CPC分类号： G06F12/0811 ,  G06F12/0837 ,  G06F12/0875

摘要： A context-information-dependent instruction causes a context-information-dependent operation to be performed based on specified context information indicative of a specified execution context. A context information translation cache 10 stores context information translation entries each specifying untranslated context information and translated context information. Lookup circuitry 14 performs a lookup of the context information translation cache based on the specified context information, to identify whether the context information translation cache includes a matching context information translation entry which is valid and which specifies untranslated context information corresponding to the specified context information. When the matching context information translation entry is identified, the context-information-dependent operation is performed based on the translated context information specified by the matching context information translation entry.

公开(公告)号：US11526443B2

公开(公告)日：2022-12-13

申请号：US17445146

申请日：2021-08-16

申请人： Arm Limited

发明人： Alexander Alfred Hornung ,  Andrew Brookfield Swaine

IPC分类号： G06F12/0802 ,  G06F3/06

摘要： Requester circuitry 4 issues an access request specifying a target physical address (PA) and a target physical address space (PAS) identifier identifying a target PAS. Prior to a point of physical aliasing (PoPA), a pre-PoPA memory system component 24, 8 treats aliasing PAs from different PASs which actually correspond to the same memory system resource as if they correspond to different memory system resources. A post-PoPA memory system component 6 treats the aliasing PAs as referring to the same memory system resource. When the target PA and target PAS of a read-if-hit-pre-PoPA request hit in a pre-PoPA cache 24, a data response is returned to the requester circuitry 4. If the read-if-hit-pre-PoPA request misses in the pre-PoPA cache 24, a no-data response is returned. The read-if-hit-pre-PoPA request is safe to issue speculatively while waiting for security checks to be performed, improving performance.

公开(公告)号：US10664399B2

公开(公告)日：2020-05-26

申请号：US15825633

申请日：2017-11-29

申请人： ARM Limited

发明人： Håkan Lars-Göran Persson ,  Ian Rudolf Bratt ,  Andrew Brookfield Swaine ,  Bruce James Mathewson

IPC分类号： G06F12/0831 ,  G06F13/16

摘要： A filter comprises interface circuitry, to intercept coherency protocol transactions exchanged between a master device comprising a first cache and an interconnect for managing coherency between the first cache and at least one other cache or other master device. The filter has filtering circuitry for filtering the coherency protocol transactions in dependence on memory access permission data defining which regions of an address space the master device is allowed to access.

公开(公告)号：US10255195B2

公开(公告)日：2019-04-09

申请号：US15614644

申请日：2017-06-06

申请人： ARM LIMITED

发明人： Michal Karol Bogusz ,  Quinn Carter ,  Andrew Brookfield Swaine

IPC分类号： G06F12/10 ,  G06F12/1027 ,  G06F12/02 ,  G06F12/1009

摘要： An apparatus, system, and method for address translation are provided. Physical address information corresponding to virtual addresses is prefetched and stored, where at least some sequences of the virtual addresses are in a predefined order. The physical address information is prefetched based on identification information provided by a data processing activity, comprising at least a segment identifier and a portion of a virtual address to be translated. The storage has segments of entries, wherein each segment stores physical address information which corresponds to virtual addresses in a predefined order. This predefined order means that it is not necessary to store virtual addresses in the storage. Storage capacity and response speed are therefore gained.

公开(公告)号：US11755497B2

公开(公告)日：2023-09-12

申请号：US17197425

申请日：2021-03-10

申请人： Arm Limited

发明人： Andrew Brookfield Swaine

IPC分类号： G06F12/1027

CPC分类号： G06F12/1027 ,  G06F2212/45

摘要： Memory management apparatus comprises input circuitry to receive a translation request defining a first memory address within a first memory address space; prediction circuitry to generate a predicted second memory address within a second memory address space as a predicted translation of the first memory address, the predicted second memory address being a predetermined function of the first memory address; control circuitry to initiate processing of the predicted second memory address; translation and permission circuitry to perform an operation to generate a translated second memory address for the first memory address associated with permission information to indicate whether memory access is permitted to the translated second memory address; and output circuitry to provide the translated second memory address as a response to the translation request when the permission information indicates that access is permitted to the translated second memory address.

公开(公告)号：US11531624B2

公开(公告)日：2022-12-20

申请号：US15007529

申请日：2016-01-27

申请人： ARM Limited

发明人： Viswanath Chakrala ,  Andrew Brookfield Swaine

IPC分类号： G06F12/1027

摘要： Apparatus for data processing and a method of data processing are provided. Address translation storage stores address translations between first set addresses and second set addresses, and responds to a request comprising a first set address to return a response comprising a second set address if the required address translation is currently stored therein. If it is not the request is forwarded towards memory in a memory hierarchy. A pending request storage stores entries for received requests and in response to reception of the request, if a stored entry for a previous request indicates that the previous request has been forwarded towards the memory and an expected response to the previous request will provide the address translation, intercepts the request to delay its reception by the address translation storage. Bandwidth pressure on the address translation storage is thus relieved.

公开(公告)号：US10324858B2

公开(公告)日：2019-06-18

申请号：US15620017

申请日：2017-06-12

申请人： ARM LIMITED

发明人： Bruce James Mathewson ,  Phanindra Kumar Mannava ,  Matthew Lucien Evans ,  Paul Gilbert Meyer ,  Andrew Brookfield Swaine

IPC分类号： G06F12/10 ,  G06F12/1036 ,  G06F12/0802 ,  G06F12/14 ,  G06F13/16

摘要： Access control circuitry comprises: a detector to detect a memory address translation between a virtual memory address in a virtual memory address space and a physical memory address in a physical memory address space, provided in response to a translation request by further circuitry; an address translation memory, to store data representing a set of physical memory addresses previously provided to the further circuitry in response to translation requests by the further circuitry; an interface to receive a physical memory address from the further circuitry for a memory access by the further circuitry; a comparator to compare a physical memory address received from the further circuitry with the set of physical addresses stored by the address translation memory, and to permit access, by the further circuitry, to a physical address included in the set of one or more physical memory addresses.

公开(公告)号：US09229908B2

公开(公告)日：2016-01-05

申请号：US13934741

申请日：2013-07-03

申请人： ARM Limited

发明人： John Michael Horley ,  Andrew Brookfield Swaine ,  Michael John Williams

IPC分类号： G06F17/10 ,  G06F7/02 ,  G06F7/76

CPC分类号： G06F17/10 ,  G06F7/02 ,  G06F7/76 ,  G06F7/764

摘要： A data processing apparatus is provided which is configured to select 2M selected identifiers within a possible range of up to 2N identifiers, where M≦N. The data processing apparatus comprises a selection storage unit configured to store at least N+1 identifier selection bits, wherein a position of a first marker bit in the at least N+1 identifier selection bits determines M, and an identifier selection unit configured to determine the 2M selected identifiers. The 2M selected identifiers fall within a range defined by a base identifier and a ceiling identifier. N-M bits of the N+1 identifier selection bits form N-M bits of the base identifier, and M zeroes form a further M bits of the base identifier. The ceiling identifier corresponds to the base identifier, except that the M zeroes of the base identifier are replaced by M ones.

摘要翻译： 提供了一种数据处理装置，其被配置为在最多2N个标识符的可能范围内选择2M个选择的标识符，其中M＆N; E; N。 数据处理装置包括：选择存储单元，被配置为存储至少N + 1个标识符选择位，其中，所述至少N + 1个标识符选择位中的第一标记位的位置确定M;以及标识符选择单元， 2M选择的标识符。 2M个选择的标识符落在由基本标识符和上限标识符定义的范围内。 N + 1标识符选择位的N-M位形成基本标识符的N-M位，并且M个零构成基本标识符的另外M位。 天花板标识符对应于基本标识符，除了基本标识符的M个零被M 1替换。

公开(公告)号：US20140019501A1

公开(公告)日：2014-01-16

申请号：US13934741

申请日：2013-07-03

申请人： ARM Limited

发明人： John Michael HORLEY ,  Andrew Brookfield Swaine ,  Michael John Williams

IPC分类号： G06F17/10

CPC分类号： G06F17/10 ,  G06F7/02 ,  G06F7/76 ,  G06F7/764

摘要： A data processing apparatus is provided which is configured to select 2M selected identifiers within a possible range of up to 2N identifiers, where M≦N. The data processing apparatus comprises a selection storage unit configured to store at least N+1 identifier selection bits, wherein a position of a first marker bit in the at least N+1 identifier selection bits determines M, and an identifier selection unit configured to determine the 2M selected identifiers. The 2M selected identifiers fall within a range defined by a base identifier and a ceiling identifier. N-M bits of the N+1 identifier selection bits form N-M bits of the base identifier, and M zeroes form a further M bits of the base identifier. The ceiling identifier corresponds to the base identifier, except that the M zeroes of the base identifier are replaced by M ones.

摘要翻译： 提供了一种数据处理装置，其被配置为在最多2N个标识符的可能范围内选择2M个选择的标识符，其中M @ N。 数据处理装置包括：选择存储单元，被配置为存储至少N + 1个标识符选择位，其中，所述至少N + 1个标识符选择位中的第一标记位的位置确定M;以及标识符选择单元， 2M选择的标识符。 2M个选择的标识符落在由基本标识符和上限标识符定义的范围内。 N + 1标识符选择位的N-M位形成基本标识符的N-M位，并且M个零构成基本标识符的另外M位。 天花板标识符对应于基本标识符，除了基本标识符的M个零被M 1替换。