公开(公告)号：US20220147679A1

公开(公告)日：2022-05-12

申请号：US17091229

申请日：2020-11-06

Applicant: Arm Limited

Inventor： Sharath Koodali Edathil ,  Marlin Wayne Frederick, JR.

IPC: G06F30/373 ,  G06F30/394 ,  G06F30/398 ,  G06F30/327

Abstract: Various implementations described herein refer to a method. The method may be configured to synthesize standard cells for a physical design having a power supply net with power supply rails. The method may be configured to employ a place-and-route tool so as to define edge-types for each standard cell of the standard cells in the physical design based on the power supply net and the power supply rails that touch at least one edge of each standard cell of the standard cells.

公开(公告)号：US20200286548A1

公开(公告)日：2020-09-10

申请号：US16294577

申请日：2019-03-06

Applicant: Arm Limited

Inventor： Marlin Wayne Frederick, JR. ,  Ronald Paxton Preston ,  Andy Wangkun Chen ,  Yew Keong Chong

IPC: G11C11/412 ,  G11C11/419

Abstract: Various implementations described herein refer to an integrated circuit having an array of bitcells coupled between at least one pair of bitlines including a first bitline and a second bitline that is a complement of the first bitline. The integrated circuit may include at least one pair of ancillary lines disposed adjacent to the at least one pair of bitlines, and the at least one pair of ancillary lines include a first ancillary line disposed adjacent to the first bitline and a second ancillary line disposed adjacent to the second bitline. The integrated circuit may include multiple pairs of passgates coupled between the at least one pair of bitlines and the at least one pair of ancillary lines.

公开(公告)号：US20180218108A1

公开(公告)日：2018-08-02

申请号：US15418613

申请日：2017-01-27

Applicant: ARM Limited

Inventor： Ravindra Narayana Rao ,  Marlin Wayne Frederick, JR. ,  Karen Lee Delk ,  Stefan Charles Creaser

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/78

Abstract: Various implementations described herein are directed to an apparatus having a receiver module that receives a floorplan of an integrated circuit having power gates, an obstruction, and a control pin for providing a sleep signal. The apparatus may include an identifier module that identifies where the obstruction interrupts a sequence of the power gates, organizes the sequence of the power gates into a column, and divides the column into segments in which a first segment lies below the obstruction, a second segment lies above the obstruction, and a third segment is offset from the first and second segments. The apparatus may include a stitcher module that performs sleep signal stitching for the integrated circuit by distributing a sleep signal from the control pin to the power gates that includes each power gate in each of the first, second, and third segments.