公开(公告)号：US20180150297A1

公开(公告)日：2018-05-31

申请号：US15578324

申请日：2016-03-31

Applicant: ARM LIMITED

Inventor： Max John BATLEY ,  Simon John CRASKE ,  Ian Michael CAULFIELD ,  Peter Richard GREENHALGH ,  Allan John SKILLMAN ,  Antony John PENTON

IPC: G06F9/30 ,  G06F9/38 ,  G06F1/32

CPC classification number: G06F9/30145 ,  G06F1/3296 ,  G06F9/3836 ,  G06F9/3867 ,  G06F9/3885

Abstract: An apparatus (2) has a processing pipeline (4) supporting at least a first processing mode and a second processing mode with different energy consumption or performance characteristics. A storage structure (22, 30, 36, 50, 40, 64, 44) is accessible in both the first and second processing modes. When the second processing mode is selected, control circuitry (70) triggers a subset (102) of the entries of the storage structure to be placed in a power saving state.

公开(公告)号：US20170091097A1

公开(公告)日：2017-03-30

申请号：US15254233

申请日：2016-09-01

Applicant: ARM LIMITED

Inventor： Alex James WAUGH ,  Max John BATLEY ,  Thomas Edward ROBERTS

IPC: G06F12/0815 ,  G06F12/1027

Abstract: An apparatus comprises a translation lookaside buffer (TLB) comprising TLB entries for storing address translation data for translating virtual addresses to physical addresses. Hazard checking circuitry detects a hazard condition when two data access transactions correspond to the same physical address. The hazard checking circuitry includes a TLB entry identifier comparator to compare TLB entry identifiers identifying the TLB entries corresponding to the two data access transactions. The hazard condition is detected in dependence on whether the TLB entry identifiers match.

公开(公告)号：US20160357561A1

公开(公告)日：2016-12-08

申请号：US15097377

申请日：2016-04-13

Applicant: ARM LIMITED

Inventor： Peter Richard GREENHALGH ,  Simon John CRASKE ,  Ian Michael CAULFIELD ,  Max John BATLEY ,  Allan John SKILLMAN ,  Antony John PENTON

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/08

CPC classification number: G06F9/30083 ,  G06F9/30058 ,  G06F9/30101 ,  G06F9/3016 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/3867

Abstract: A processing pipeline may have first and second execution circuits having different performance or energy consumption characteristics. Instruction supply circuitry may support different instruction supply schemes with different energy consumption or performance characteristics. This can allow a further trade-off between performance and energy efficiency. Architectural state storage can be shared between the execute units to reduce the overhead of switching between the units. In a parallel execution mode, groups of instructions can be executed on both execute units in parallel.

Abstract translation: 处理管线可以具有具有不同性能或能量消耗特性的第一和第二执行电路。 指令供应电路可以支持具有不同能量消耗或性能特征的不同指令供给方案。 这可以在性能和能源效率之间进一步权衡。 建筑状态存储可以在执行单元之间共享，以减少单元之间切换的开销。 在并行执行模式中，可以在两个执行单元上并行执行指令组。

公开(公告)号：US20160139922A1

公开(公告)日：2016-05-19

申请号：US14930920

申请日：2015-11-03

Applicant: ARM LIMITED

Inventor： Simon John CRASKE ,  Alexander Alfred Hornung ,  Max John BATLEY ,  Kauser Yakub JOHAR

IPC: G06F9/30 ,  G06F9/455

CPC classification number: G06F9/30072 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/45533 ,  G06F9/522

Abstract: Apparatus for data processing and a method of data processing are provided, according to which the processing circuitry of the apparatus can access a memory system and execute data processing instructions in one context of multiple contexts which it supports. When the processing circuitry executes a barrier instruction, the resulting access ordering constraint may be limited to being enforced for accesses which have been initiated by the processing circuitry when operating in an identified context, which may for example be the context in which the barrier instruction has been executed. This provides a separation between the operation of the processing circuitry in its multiple possible contexts and in particular avoids delays in the completion of the access ordering constraint, for example relating to accesses to high latency regions of memory, from affecting the timing sensitivities of other contexts.

Abstract translation: 提供了用于数据处理的装置和数据处理方法，根据该装置，该装置的处理电路可以访问存储器系统并在其支持的多个上下文的一个上下文中执行数据处理指令。 当处理电路执行屏障指令时，所得到的访问排序约束可以被限制为对于在所识别的上下文中操作时由处理电路启动的访问被强制执行，其可以例如是屏障指令具有的上下文 被执行 这提供了处理电路在其多个可能上下文中的操作之间的间隔，并且特别地避免了访问排序约束的完成中的延迟，例如涉及对存储器的高等待时间区域的访问，从而影响其他上下文的定时灵敏度 。

公开(公告)号：US20140281423A1

公开(公告)日：2014-09-18

申请号：US13826553

申请日：2013-03-14

Applicant: ARM LIMITED

Inventor： Ian Michael CAULFIELD ,  Peter Richard GREENHALGH ,  Max John BATLEY

IPC: G06F9/30

CPC classification number: G06F9/30079 ,  G06F9/3836 ,  G06F9/3875 ,  G06F9/3885

Abstract: A processor has a processing pipeline with first, second and third stages. An instruction at the first stage takes fewer cycles to reach the second stage then the third stage. The second and third stages each have a duplicated processing resource. For a pending instruction which requires the duplicated resource and can be processed using the duplicated resource at either of the second and third stages, the first stage determines whether a required operand would be available when the pending instruction would reach the second stage. If the operand would be available, then the pending instruction is processed using the duplicated resource at the second stage, while if the operand would not be available in time then the instruction is processed using the duplicated resource in the third pipeline stage. This technique helps to reduce delays caused by data dependency hazards.

Abstract translation: 处理器具有第一，第二和第三阶段的处理流水线。 第一阶段的指令需要更少的周期才能到达第二阶段，然后到第三阶段。 第二和第三阶段各有一个重复的处理资源。 对于要求复制的资源并且可以使用第二级和第三级中的任一级的重复资源来处理的等待指令，第一级确定当待命指令将到达第二级时所需的操作数是否可用。 如果操作数可用，则在第二阶段使用重复的资源处理挂起的指令，而如果操作数在时间上不可用，则使用第三流水线阶段中的重复资源处理指令。 这种技术有助于减少数据依赖性危害造成的延误。