公开(公告)号：US20170091097A1

公开(公告)日：2017-03-30

申请号：US15254233

申请日：2016-09-01

Applicant: ARM LIMITED

Inventor： Alex James WAUGH ,  Max John BATLEY ,  Thomas Edward ROBERTS

IPC: G06F12/0815 ,  G06F12/1027

Abstract: An apparatus comprises a translation lookaside buffer (TLB) comprising TLB entries for storing address translation data for translating virtual addresses to physical addresses. Hazard checking circuitry detects a hazard condition when two data access transactions correspond to the same physical address. The hazard checking circuitry includes a TLB entry identifier comparator to compare TLB entry identifiers identifying the TLB entries corresponding to the two data access transactions. The hazard condition is detected in dependence on whether the TLB entry identifiers match.

公开(公告)号：US20170293567A1

公开(公告)日：2017-10-12

申请号：US15632654

申请日：2017-06-26

Applicant: ARM LIMITED

Inventor： Richard F. BRYANT ,  Kim Richard SCHUTTENBERG ,  Lilian Atieno HUTCHINS ,  Thomas Edward ROBERTS ,  Alex James WAUGH ,  Max John BATLEY

IPC: G06F12/1027 ,  G06F12/1036 ,  G06F9/30 ,  G06F12/1009 ,  G06F9/46

CPC classification number: G06F12/1027 ,  G06F9/30043 ,  G06F9/467 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/1009 ,  G06F12/1036 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/682

Abstract: An apparatus comprises processing circuitry to process data access operations specifying a virtual address of data to be loaded from or stored to a data store, and proxy identifier determining circuitry to determine a proxy identifier for a data access operation to be processed by the data access circuitry, the proxy identifier having fewer bits than a physical address corresponding to the virtual address specified by the data access operation. The processing circuitry comprises at least one buffer to buffer information (including the proxy identifier) associated with one or more pending data access operations awaiting processing. Address translation circuitry determines the physical address corresponding to the virtual address specified for a data access operation after that data access operation has progressed beyond said at least one buffer.

公开(公告)号：US20170249085A1

公开(公告)日：2017-08-31

申请号：US15440254

申请日：2017-02-23

Applicant: ARM Limited

Inventor： Cédric Denis Robert AIRAUD ,  Max John BATLEY ,  Ian Michael CAULFIELD ,  Thomas Edward ROBERTS

IPC: G06F3/06 ,  G06F12/06

CPC classification number: G06F3/0604 ,  G06F3/061 ,  G06F3/0638 ,  G06F3/0673 ,  G06F12/0223 ,  G06F12/0646 ,  G06F12/0893 ,  G06F2212/1016 ,  G06F2212/1028 ,  Y02D10/13

Abstract: Data storage apparatus comprises detection circuitry configured to detect a match between a multi-bit reference memory address and a test address, the test address being a combination of a multi-bit base address and a multi-bit address offset, the detection circuitry comprising: a comparator configured to compare, as a first comparison, a first subset of bits of the reference memory address with a combination of the corresponding first subset of bits of the base address and the corresponding first subset of bits of the address offset; the comparator being configured to compare, as a second comparison, a second, different subset of bits of the reference memory address with the corresponding second subset of bits of the base address; a detector configured to detect the match between the reference memory address and the test address when both of the first comparison and the second comparison detect a respective match; and control circuitry configured to control operation of the data storage apparatus in dependence upon the reference memory address when a match is detected by the detector.