公开(公告)号：US20240028241A1

公开(公告)日：2024-01-25

申请号：US17871332

申请日：2022-07-22

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Steven Daniel MACLEAN ,  Nicholas Andrew PLANTE ,  Muhammad Umar FAROOQ ,  Michael Brian SCHINZLER ,  Nicholas Todd HUMPHRIES ,  Glen Andrew HARRIS

IPC: G06F3/06

CPC classification number: G06F3/065 ,  G06F3/0604 ,  G06F3/0673

Abstract: There is provided a data processing apparatus in which decode circuitry receives a memory copy instruction containing an indication of a source area of memory, an indication of a destination area of memory, and an indication of a remaining copy length. In response to receiving the memory copy instruction, the decode circuitry generates at least one active memory copy operation or a null memory copy operation. The active memory copy operation causes one or more execution units to perform a memory copy from part of the source area of memory to part of the destination area of memory and the null memory copy operation leaves the destination area of memory unmodified.

公开(公告)号：US20230195466A1

公开(公告)日：2023-06-22

申请号：US17554573

申请日：2021-12-17

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Muhammad Umar FAROOQ ,  William Elton BURKY ,  Michael Brian SCHINZLER ,  Jason Lee SETTER ,  David Gum LIM

IPC: G06F9/38

CPC classification number: G06F9/384 ,  G06F9/3867

Abstract: A data processing apparatus is provided that comprises rename circuitry for performing a register rename stage of a pipeline in respect of a stream of operations. Move elimination circuitry performs a move elimination operation on the stream of operations in which a move operation is eliminated and the register rename stage performs an adjustment of an identity of registers in the stream of operations to compensate for the move operation being eliminated and demotion circuitry reverses or inhibits the adjustment in response to one or more conditions being met.

公开(公告)号：US20210064533A1

公开(公告)日：2021-03-04

申请号：US16552001

申请日：2019-08-27

Applicant: Arm Limited

Inventor： Michael Brian SCHINZLER ,  Michael FILIPPO

IPC: G06F12/0875

Abstract: A data processing apparatus is provided. The data processing apparatus includes fetch circuitry to fetch instructions from storage circuitry. Decode circuitry decodes each of the instructions into one or more operations and provides the one or more operations to one or more execution units. The decode circuitry is adapted to decode at least one of the instructions into a plurality of operations. Cache circuitry caches the one or more operations and at least one entry of the cache circuitry is a compressed entry that represents the plurality of operations.