公开(公告)号：US20240028241A1

公开(公告)日：2024-01-25

申请号：US17871332

申请日：2022-07-22

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Steven Daniel MACLEAN ,  Nicholas Andrew PLANTE ,  Muhammad Umar FAROOQ ,  Michael Brian SCHINZLER ,  Nicholas Todd HUMPHRIES ,  Glen Andrew HARRIS

IPC: G06F3/06

CPC classification number: G06F3/065 ,  G06F3/0604 ,  G06F3/0673

Abstract: There is provided a data processing apparatus in which decode circuitry receives a memory copy instruction containing an indication of a source area of memory, an indication of a destination area of memory, and an indication of a remaining copy length. In response to receiving the memory copy instruction, the decode circuitry generates at least one active memory copy operation or a null memory copy operation. The active memory copy operation causes one or more execution units to perform a memory copy from part of the source area of memory to part of the destination area of memory and the null memory copy operation leaves the destination area of memory unmodified.