公开(公告)号：US11900995B2

公开(公告)日：2024-02-13

申请号：US17223950

申请日：2021-04-06

Applicant: Arm Limited

Inventor： Rajiv Kumar Sisodia ,  Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Ayush Kulshrestha ,  Munish Kumar

IPC: G11C11/419 ,  G11C11/418 ,  G11C11/412

CPC classification number: G11C11/418 ,  G11C11/412 ,  G11C11/419

Abstract: Various implementations described herein are related to a method for accessing a bitcell in an array of bitcells with a wordline and a bitline. The method may perform a precharge operation on the bitline that precharges the bitline after a read cycle and before a write cycle. Also, the method may extend precharge time of the precharge operation between the read cycle and the write cycle, e.g., by modulating a wordline signal on the wordline with early cut-off of the wordline signal on the wordline during the read cycle.

公开(公告)号：US11514979B2

公开(公告)日：2022-11-29

申请号：US17218949

申请日：2021-03-31

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Munish Kumar ,  Ayush Kulshrestha ,  Rajiv Kumar Sisodia ,  Yew Keong Chong ,  Kumaraswamy Ramanathan ,  Edward Martin McCombs, Jr.

IPC: G11C8/00 ,  G11C11/418 ,  G11C11/16

Abstract: Various implementations described herein are related to a device with a wordline driver that provides a wordline signal to a wordline based on a row selection signal and a row clock signal. The device may have row selector logic that provides the row selection signal to the wordline driver based on first input signals in a periphery voltage domain. The device may also have level shifter circuitry that provides the row clock signal to the wordline driver in a core voltage domain based on second input signals in the periphery voltage domain.

公开(公告)号：US20210193195A1

公开(公告)日：2021-06-24

申请号：US16725779

申请日：2019-12-23

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Munish Kumar

IPC: G11C7/10

Abstract: Various implementations described herein are related to a device having memory circuitry and multiplexer circuitry. The memory circuitry may include a single bank of memory cells that are arranged in multiple columns, and each column of the multiple columns may provide singe-bit data. The multiplexer circuitry may include multiplexer logic that receives the single-bit data from each column of the multiple columns and provides selected data as output data.

公开(公告)号：US10978141B1

公开(公告)日：2021-04-13

申请号：US16698851

申请日：2019-11-27

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Andy Wangkun Chen ,  Vivek Asthana ,  Munish Kumar

IPC: G11C11/418 ,  G11C11/417 ,  G11C11/419

Abstract: According to one implementation of the present disclosure, an integrated circuit includes first and second word-line decoder circuitry, two or more memory instances coupled to the first and second word-line decoder circuitry; and a control block circuitry coupled to the first and second word-line decoder circuitry and the two or more memory instances. Also, a pin bus enabled in the control block circuitry may be configured to at least partially control selection of one or more of the two or more memory instances.

公开(公告)号：US10763267B2

公开(公告)日：2020-09-01

申请号：US16244047

申请日：2019-01-09

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Munish Kumar

IPC: H01L27/11 ,  H01L27/02 ,  G11C11/419 ,  H01L23/528 ,  G11C11/418

Abstract: Various implementations described herein refer to an integrated circuit having a memory structure with a two-bitcell layout and a four cell poly pitch. The two-bitcell layout includes a first bitcell and a second bitcell with structural contours that are joined together in a coupling arrangement. The first bitcell and the second bitcell have multiple transistors that are arranged to store data during write operations and allow access of data during read operations.