公开(公告)号：US12068025B2

公开(公告)日：2024-08-20

申请号：US17856928

申请日：2022-07-01

申请人： Arm Limited

发明人： Rahul Mathur ,  Edward Martin McCombs, Jr. ,  Hsin-Yu Chen

IPC分类号： G11C11/00 ,  G11C11/412 ,  G11C11/418

CPC分类号： G11C11/418 ,  G11C11/412

摘要： Various implementations described herein are directed to a device having memory with banks of bitcells with each bank having a bitcell array. The device may have header circuitry that powers-up a selected bank and powers-down unselected banks during a wake-up mode of operation. In some instances, only the selected bank of the memory is powered-up with the header circuitry during the wake-up mode of operation.

公开(公告)号：US11967360B2

公开(公告)日：2024-04-23

申请号：US17482298

申请日：2021-09-22

申请人： Arm Limited

发明人： Edward Martin McCombs, Jr.

IPC分类号： G11C7/10 ,  G11C11/4072 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096

CPC分类号： G11C11/4087 ,  G11C11/4072 ,  G11C11/4085 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096

摘要： Various implementations described herein are directed to a method. The method may receive an address to access data stored in memory. The method may enable a data access pipeline to perform memory access operations so as to access the data stored in the memory based on the address. The method may dynamically adjust the data access pipeline during the memory access operations so as to output the data based on the address.

公开(公告)号：US12087353B2

公开(公告)日：2024-09-10

申请号：US17885709

申请日：2022-08-11

申请人： Arm Limited

发明人： Edward Martin McCombs, Jr. ,  Andrew David Tune ,  Sean James Salisbury ,  Rahul Mathur ,  Hsin-Yu Chen ,  Phani Raja Bhushan Chalasani

IPC分类号： G11C11/00 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

CPC分类号： G11C11/4096 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094

摘要： A burst read with flexible burst length for on-chip memory, such as, for example, system cache memory, hierarchical cache memory, system memory, etc. is provided. Advantageously, successive burst reads are performed with less signal toggling and fewer bitline swings.

公开(公告)号：US11935580B2

公开(公告)日：2024-03-19

申请号：US17530095

申请日：2021-11-18

申请人： Arm Limited

发明人： Edward Martin McCombs, Jr. ,  Hsin-Yu Chen

IPC分类号： G11C7/12 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094

CPC分类号： G11C11/4091 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4094

摘要： One implementation described herein is related to a device having memory with sense amplifiers and precharge blocks arranged in an array with a first side and a second side. The first side has first sense amplifiers and first precharge blocks coupled together with first bitlines, and the second side has second sense amplifiers and second precharge blocks coupled together with second bitlines. The device has a first delay block coupled to the first precharge blocks in the first side of the array, and the first delay block delays precharge of the first bitlines with a first precharge burst in a multi-burst precharge event. The device has a second delay block coupled to the second precharge blocks in the second side of the array, and the second delay block delays precharge of the second bitlines with a second precharge burst in the multi-burst precharge event.

公开(公告)号：US11514979B2

公开(公告)日：2022-11-29

申请号：US17218949

申请日：2021-03-31

申请人： Arm Limited

发明人： Andy Wangkun Chen ,  Munish Kumar ,  Ayush Kulshrestha ,  Rajiv Kumar Sisodia ,  Yew Keong Chong ,  Kumaraswamy Ramanathan ,  Edward Martin McCombs, Jr.

IPC分类号： G11C8/00 ,  G11C11/418 ,  G11C11/16

摘要： Various implementations described herein are related to a device with a wordline driver that provides a wordline signal to a wordline based on a row selection signal and a row clock signal. The device may have row selector logic that provides the row selection signal to the wordline driver based on first input signals in a periphery voltage domain. The device may also have level shifter circuitry that provides the row clock signal to the wordline driver in a core voltage domain based on second input signals in the periphery voltage domain.