公开(公告)号：US12243622B2

公开(公告)日：2025-03-04

申请号：US17885753

申请日：2022-08-11

Applicant: Arm Limited

Inventor： Edward Martin McCombs, Jr.

IPC: G11C8/08 ,  G06F1/3234 ,  G11C5/14 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C8/18 ,  G11C11/4072 ,  G11C11/408

Abstract: Dynamic power management for an on-chip memory, such as a system cache memory as well as other memories, is provided. The memory includes wordline sections, input/output (I/O) circuitry, and control circuitry. Each wordline section includes a number of wordlines, and each wordline section is coupled to a different wordline control circuitry. The control circuitry is configured to, in response to receiving an access request including an address, decode the address including determine, based on the address, an associated wordline, and determine, based on the associated wordline, an associated wordline section. The control circuitry is further configured to apply power to wordline control circuitry coupled to the associated wordline section.

公开(公告)号：US12174738B2

公开(公告)日：2024-12-24

申请号：US17885780

申请日：2022-08-11

Applicant: Arm Limited

Inventor： Andrew David Tune ,  Sean James Salisbury ,  Edward Martin McCombs, Jr.

IPC: G06F12/0802

Abstract: Circuitry including cache storage and control circuitry is provided. The cache storage includes an array of random access memory storage elements, and is configured to store data in multiple cache sectors, each cache sector including a number of cache storage data units. The control circuitry is configured to control access to the cache storage including, for example, accessing the cache storage data units in the cache sectors. After accessing a cache storage data unit in a cache sector, the energy requirement and/or latency for the next access to a cache storage data unit in the same sector is lower than the energy requirement and/or latency for the next access to a cache storage data unit in a different same sector.

公开(公告)号：US12068025B2

公开(公告)日：2024-08-20

申请号：US17856928

申请日：2022-07-01

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Edward Martin McCombs, Jr. ,  Hsin-Yu Chen

IPC: G11C11/00 ,  G11C11/412 ,  G11C11/418

CPC classification number: G11C11/418 ,  G11C11/412

Abstract: Various implementations described herein are directed to a device having memory with banks of bitcells with each bank having a bitcell array. The device may have header circuitry that powers-up a selected bank and powers-down unselected banks during a wake-up mode of operation. In some instances, only the selected bank of the memory is powered-up with the header circuitry during the wake-up mode of operation.

公开(公告)号：US11967360B2

公开(公告)日：2024-04-23

申请号：US17482298

申请日：2021-09-22

Applicant: Arm Limited

Inventor： Edward Martin McCombs, Jr.

IPC: G11C7/10 ,  G11C11/4072 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C11/4087 ,  G11C11/4072 ,  G11C11/4085 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096

Abstract: Various implementations described herein are directed to a method. The method may receive an address to access data stored in memory. The method may enable a data access pipeline to perform memory access operations so as to access the data stored in the memory based on the address. The method may dynamically adjust the data access pipeline during the memory access operations so as to output the data based on the address.

公开(公告)号：US12249400B2

公开(公告)日：2025-03-11

申请号：US17885747

申请日：2022-08-11

Applicant: Arm Limited

Inventor： Edward Martin McCombs, Jr.

IPC: G11C16/04 ,  G11C7/10 ,  G11C8/08 ,  G11C8/18

Abstract: An on-chip memory is provided. The memory includes wordline sections, input/output (I/O) circuitry, and control circuitry. Each wordline section includes a number of wordlines, and each wordline section is coupled to a different wordline control circuitry. The control circuitry is configured to, in response to receiving an access request including an address, decode the address including determine, based on the address, an associated wordline, and determine, based on the associated wordline, an associated wordline section. The control circuitry is further configured to apply power to wordline control circuitry coupled to the associated wordline section, and access the address.

公开(公告)号：US12087353B2

公开(公告)日：2024-09-10

申请号：US17885709

申请日：2022-08-11

Applicant: Arm Limited

Inventor： Edward Martin McCombs, Jr. ,  Andrew David Tune ,  Sean James Salisbury ,  Rahul Mathur ,  Hsin-Yu Chen ,  Phani Raja Bhushan Chalasani

IPC: G11C11/00 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C11/4096 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094

Abstract: A burst read with flexible burst length for on-chip memory, such as, for example, system cache memory, hierarchical cache memory, system memory, etc. is provided. Advantageously, successive burst reads are performed with less signal toggling and fewer bitline swings.

公开(公告)号：US11935580B2

公开(公告)日：2024-03-19

申请号：US17530095

申请日：2021-11-18

Applicant: Arm Limited

Inventor： Edward Martin McCombs, Jr. ,  Hsin-Yu Chen

IPC: G11C7/12 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/4091 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4094

Abstract: One implementation described herein is related to a device having memory with sense amplifiers and precharge blocks arranged in an array with a first side and a second side. The first side has first sense amplifiers and first precharge blocks coupled together with first bitlines, and the second side has second sense amplifiers and second precharge blocks coupled together with second bitlines. The device has a first delay block coupled to the first precharge blocks in the first side of the array, and the first delay block delays precharge of the first bitlines with a first precharge burst in a multi-burst precharge event. The device has a second delay block coupled to the second precharge blocks in the second side of the array, and the second delay block delays precharge of the second bitlines with a second precharge burst in the multi-burst precharge event.

公开(公告)号：US11514979B2

公开(公告)日：2022-11-29

申请号：US17218949

申请日：2021-03-31

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Munish Kumar ,  Ayush Kulshrestha ,  Rajiv Kumar Sisodia ,  Yew Keong Chong ,  Kumaraswamy Ramanathan ,  Edward Martin McCombs, Jr.

IPC: G11C8/00 ,  G11C11/418 ,  G11C11/16

Abstract: Various implementations described herein are related to a device with a wordline driver that provides a wordline signal to a wordline based on a row selection signal and a row clock signal. The device may have row selector logic that provides the row selection signal to the wordline driver based on first input signals in a periphery voltage domain. The device may also have level shifter circuitry that provides the row clock signal to the wordline driver in a core voltage domain based on second input signals in the periphery voltage domain.