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    LOW-POWER, ALWAYS-LISTENING, VOICE COMMAND DETECTION AND CAPTURE
    11.
    发明申请
    LOW-POWER, ALWAYS-LISTENING, VOICE COMMAND DETECTION AND CAPTURE 审中-公开

    公开(公告)号：US20180174583A1

    公开(公告)日：2018-06-21

    申请号：US15706178

    申请日：2017-09-15

    Applicant: Avnera Corporation

    Inventor： Xudong Zhao ,  Alexander C. Stange ,  Shawn O'Connor ,  Ali Hadiashar

    IPC: G10L15/22 ,  G10L25/78 ,  G10L25/84 ,  H03M3/00

    CPC classification number: G10L15/22 ,  G10L25/78 ,  G10L25/84 ,  G10L2015/088 ,  G10L2025/783 ,  H03M3/458

    Abstract: A system for detecting and capturing voice commands, the system comprising a voice-activity detector (VAD) configured to receive a VAD-received digital-audio signal; determine the amplitude of the VAD-received digital-audio signal; compare the amplitude of the VAD-received digital-audio signal to a first threshold and to a second threshold; withhold a VAD interrupt signal when the amplitude of the VAD-received digital-audio signal does not exceed the first threshold or the second threshold; generate the VAD interrupt signal when the amplitude of the VAD-received digital-audio signal exceeds the first threshold and the second threshold; and perform spectral analysis of the VAD-received digital-audio signal when the amplitude of the VAD-received digital-audio signal is between the first threshold and the second threshold.

    RATE CONVERTOR
    14.
    发明申请
    RATE CONVERTOR 有权
    速率转换器

    公开(公告)号：US20160140983A1

    公开(公告)日：2016-05-19

    申请号：US14857681

    申请日：2015-09-17

    Applicant: AVNERA CORPORATION

    Inventor： Xudong Zhao

    IPC: G10L21/043 ,  G10L19/008 ,  G10L21/0232 ,  G10L19/02 ,  G10L19/24 ,  G10L21/0224

    CPC classification number: H03H17/0628 ,  G10L19/00 ,  G10L19/24 ,  G10L21/0316 ,  G10L21/0356 ,  G10L2019/001 ,  H03H17/028 ,  H03M5/00 ,  H03M7/00 ,  H03M13/00 ,  H03M13/27 ,  H03M13/33

    Abstract: Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.

    Abstract translation: 本发明的实施例可以用于实现速率转换器，其包括：正向（音频）路径中的6个信道，每个信道具有每信道24位信号路径，110dB的端到端SNR，全部在 20 Hz至20 KHz带宽。 实施例还可以用于实现速率转换器，其具有：在反向路径中的2个信道，例如用于语音信号，每信道16位信号路径，93dB的端到端SNR，均在20Hz至20 KHz带宽。 速率转换器可以包括诸如8,11.025,12,16,22.05,24,34,44,48和96KHz的采样率。 此外，根据实施例的速率转换器可以包括低功率模式的门控时钟以节省功率。

    Acoustic processor having low latency
    15.
    发明授权
    Acoustic processor having low latency 有权

    公开(公告)号：US10997960B2

    公开(公告)日：2021-05-04

    申请号：US16545917

    申请日：2019-08-20

    Applicant: Avnera Corporation

    Inventor： Amit Kumar ,  Thomas Irrgang ,  Xudong Zhao

    IPC: H04R3/00 ,  G10K11/178 ,  H04R1/10

    Abstract: An audio processing system can include an Analog to Digital Converter structured to receive an analog input signal and convert the analog input signal to a digital input signal, a first processor coupled with the Analog to Digital Converter, the first processor including at least one programmable bi-quadratic filter chain structured to receive the digital input signal from the Analog to Digital Converter and perform audio processing on the received digital input signal at a first clock rate, and a second processor coupled with the first processor and the Analog to Digital Converter and structured to receive the digital input signal from the Analog to Digital Converter and perform audio processing on the received digital input signal at a second clock rate that is different from the first clock rate.

    Low power synchronous data interface
    16.
    发明授权
    Low power synchronous data interface 有权

    公开(公告)号：US10667056B2

    公开(公告)日：2020-05-26

    申请号：US15599331

    申请日：2017-05-18

    Applicant: Avnera Corporation

    Inventor： Chris O'Connor ,  Xudong Zhao

    IPC: H04R3/12 ,  H04R1/10 ,  H04R29/00 ,  H04R5/04 ,  G10L19/012

    Abstract: A low power, digital audio interface includes support for variable length coding depending on content of the audio data sent from the interface. A particularized coding system is implemented that uses techniques of silence detection, dynamic scaling, and periodic encoding to reduce sent data to a minimum. Other techniques include variable packet scaling based on an audio sample rate. Differential signaling techniques are also used. The digital audio interface may be used in a headphone interface to drive digital headphones. A detector in the interface may detect whether digital or analog headphones are coupled to a headphone jack and drive the headphone jack accordingly.

    ACOUSTIC PROCESSOR HAVING LOW LATENCY
    17.
    发明申请
    ACOUSTIC PROCESSOR HAVING LOW LATENCY 审中-公开

    公开(公告)号：US20200084541A1

    公开(公告)日：2020-03-12

    申请号：US16545917

    申请日：2019-08-20

    Applicant: Avnera Corporation

    Inventor： Amit Kumar ,  Thomas Irrgang ,  Xudong Zhao

    IPC: H04R3/00 ,  G10K11/178 ,  H04R1/10

    Abstract: An audio processing system can include an Analog to Digital Converter structured to receive an analog input signal and convert the analog input signal to a digital input signal, a first processor coupled with the Analog to Digital Converter, the first processor including at least one programmable bi-quadratic filter chain structured to receive the digital input signal from the Analog to Digital Converter and perform audio processing on the received digital input signal at a first clock rate, and a second processor coupled with the first processor and the Analog to Digital Converter and structured to receive the digital input signal from the Analog to Digital Converter and perform audio processing on the received digital input signal at a second clock rate that is different from the first clock rate.

    Acoustic processor having low latency
    18.
    发明授权
    Acoustic processor having low latency 有权

    公开(公告)号：US10390135B2

    公开(公告)日：2019-08-20

    申请号：US15895591

    申请日：2018-02-13

    Applicant: Avnera Corporation

    Inventor： Amit Kumar ,  Thomas Irrgang ,  Xudong Zhao

    IPC: H04R3/00 ,  G10K11/178 ,  H04R1/10

    Abstract: An audio system can include an analog portion having multiple input sensors and an output device, a first digital portion running at a first rate and having a first processor that is electrically coupled with the input sensors and the output device, and a second digital portion running at a second rate that is higher than the first rate and having a second processor that is electrically coupled with the first processor.

    LOW POWER SYNCHRONOUS DATA INTERFACE
    20.
    发明申请
    LOW POWER SYNCHRONOUS DATA INTERFACE 审中-公开

    公开(公告)号：US20170257702A1

    公开(公告)日：2017-09-07

    申请号：US15599331

    申请日：2017-05-18

    Applicant: Avnera Corporation

    Inventor： Chris O'Connor ,  Xudong Zhao

    IPC: H04R3/12 ,  H04R1/10

    Abstract: A low power, digital audio interface includes support for variable length coding depending on content of the audio data sent from the interface. A particularized coding system is implemented that uses techniques of silence detection, dynamic scaling, and periodic encoding to reduce sent data to a minimum. Other techniques include variable packet scaling based on an audio sample rate. Differential signaling techniques are also used. The digital audio interface may be used in a headphone interface to drive digital headphones. A detector in the interface may detect whether digital or analog headphones are coupled to a headphone jack and drive the headphone jack accordingly.

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