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公开(公告)号：US20180198430A1
公开(公告)日：2018-07-12
申请号：US15858101
申请日：2017-12-29
Applicant: Avnera Corporation
Inventor： Garry N. Link , Eric King , Xudong Zhao , Wai Lee , Alexander C. Stange , Amit Kumar
CPC classification number: H03G3/004 , H03F1/025 , H03F1/305 , H03F3/187 , H03F2200/507 , H03F2200/511 , H03G3/32
Abstract: A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.
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公开(公告)号：US10425053B2
公开(公告)日：2019-09-24
申请号：US15858101
申请日：2017-12-29
Applicant: Avnera Corporation
Inventor： Garry N. Link , Eric King , Xudong Zhao , Wai Lee , Alexander C. Stange , Amit Kumar
Abstract: A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.
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公开(公告)号：US20190207575A1
公开(公告)日：2019-07-04
申请号：US16295987
申请日：2019-03-07
Applicant: Avnera Corporation
Inventor： Garry N. Link , Eric King , Xudong Zhao , Wai Lee , Alexander C. Stange , Amit Kumar
CPC classification number: H03G3/004 , H03F1/025 , H03F1/305 , H03F3/187 , H03F2200/507 , H03F2200/511 , H03G3/32
Abstract: A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.
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公开(公告)号：US10230352B2
公开(公告)日：2019-03-12
申请号：US15786500
申请日：2017-10-17
Applicant: Avnera Corporation
Inventor： Xudong Zhao
IPC: G10L21/00 , G10L19/00 , H03M13/33 , H03M13/00 , H03M13/27 , H03H17/06 , G10L21/0316 , H03M7/00 , H03M5/00 , G10L21/0356 , H03H17/02 , G10L19/24
Abstract: Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.
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公开(公告)号：US10230343B2
公开(公告)日：2019-03-12
申请号：US15858101
申请日：2017-12-29
Applicant: Avnera Corporation
Inventor： Garry N. Link , Eric King , Xudong Zhao , Wai Lee , Alexander C. Stange , Amit Kumar
Abstract: A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.
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Patent Agency Ranking
公开(公告)号：US09793879B2
公开(公告)日：2017-10-17
申请号：US14857681
申请日：2015-09-17
Applicant: Avnera Corporation
Inventor： Xudong Zhao
IPC: G10L21/00 , G10L19/00 , H03M13/33 , H03M13/00 , H03M13/27 , H03H17/06 , G10L21/0316 , H03M7/00 , H03M5/00 , G10L21/0356 , H03H17/02 , G10L19/24
CPC classification number: H03H17/0628 , G10L19/00 , G10L19/24 , G10L21/0316 , G10L21/0356 , G10L2019/001 , H03H17/028 , H03M5/00 , H03M7/00 , H03M13/00 , H03M13/27 , H03M13/33
Abstract: Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.
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公开(公告)号：US20170034619A1
公开(公告)日：2017-02-02
申请号：US15294556
申请日：2016-10-14
Applicant: Avnera Corporation
Inventor： Amit Kumar , Thomas Irrgang , Xudong Zhao
IPC: H04R3/00 , G10K11/178
CPC classification number: H04R3/005 , G10K11/178 , G10K2210/3028 , G10K2210/3051 , G10K2210/3056 , H04R1/1083 , H04R2410/05
Abstract: An audio system having low latency includes a digital audio processor as well as sensor inputs coupled to the processor. The sensor inputs may be microphone inputs. The audio processor operates at the same frequency as the sensor inputs, which is typically much higher than an audio signal provided to the audio processor. In some aspects the audio processor operates as a noise cancellation processor and does not include an audio input.
Abstract translation: 具有低延迟的音频系统包括数字音频处理器以及耦合到处理器的传感器输入。 传感器输入可以是麦克风输入。 音频处理器的工作频率与传感器输入的频率相同，传感器输入通常远高于提供给音频处理器的音频信号。 在一些方面，音频处理器用作噪声消除处理器，并且不包括音频输入。
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公开(公告)号：US11677383B2
公开(公告)日：2023-06-13
申请号：US16296669
申请日：2019-03-08
Applicant: AVNERA CORPORATION
Inventor： Xudong Zhao
IPC: G10L21/0316 , H03H17/06 , H03M13/33 , H03M13/00 , H03M13/27 , H03M7/00 , H03M5/00 , G10L21/0356 , H03H17/02 , G10L19/24 , G10L19/00
CPC classification number: H03H17/0628 , G10L21/0316 , G10L21/0356 , H03H17/028 , H03M5/00 , H03M7/00 , H03M13/00 , H03M13/27 , H03M13/33 , G10L19/00 , G10L19/24 , G10L2019/001
Abstract: Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.
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公开(公告)号：US10403279B2
公开(公告)日：2019-09-03
申请号：US15706178
申请日：2017-09-15
Applicant: Avnera Corporation
Inventor： Xudong Zhao , Alexander C. Stange , Shawn O'Connor , Ali Hadiashar
Abstract: A system for detecting and capturing voice commands, the system comprising a voice-activity detector (VAD) configured to receive a VAD-received digital-audio signal; determine the amplitude of the VAD-received digital-audio signal; compare the amplitude of the VAD-received digital-audio signal to a first threshold and to a second threshold; withhold a VAD interrupt signal when the amplitude of the VAD-received digital-audio signal does not exceed the first threshold or the second threshold; generate the VAD interrupt signal when the amplitude of the VAD-received digital-audio signal exceeds the first threshold and the second threshold; and perform spectral analysis of the VAD-received digital-audio signal when the amplitude of the VAD-received digital-audio signal is between the first threshold and the second threshold.
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公开(公告)号：US09894438B2
公开(公告)日：2018-02-13
申请号：US15294556
申请日：2016-10-14
Applicant: Avnera Corporation
Inventor： Amit Kumar , Thomas Irrgang , Xudong Zhao
IPC: A61F11/06 , H04R3/00 , G10K11/178
CPC classification number: H04R3/005 , G10K11/178 , G10K2210/3028 , G10K2210/3051 , G10K2210/3056 , H04R1/1083 , H04R2410/05
Abstract: An audio system having low latency includes a digital audio processor as well as sensor inputs coupled to the processor. The sensor inputs may be microphone inputs. The audio processor operates at the same frequency as the sensor inputs, which is typically much higher than an audio signal provided to the audio processor. In some aspects the audio processor operates as a noise cancellation processor and does not include an audio input.
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