公开(公告)号：US20210096873A1

公开(公告)日：2021-04-01

申请号：US16584701

申请日：2019-09-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul James Moyer ,  Douglas Benson Hunt ,  Kai Troester

IPC: G06F9/38

Abstract: Systems, apparatuses, and methods for arbitrating threads in a computing system are disclosed. A computing system includes a processor with multiple cores, each capable of simultaneously processing instructions of multiple threads. When a thread throttling unit receives an indication that a shared cache has resource contention, the throttling unit sets a threshold number of cache misses for the cache. If the number of cache misses exceeds this threshold, then the throttling unit notifies a particular upstream computation unit to throttle the processing of instructions for the thread. After a time period elapses, if the cache continues to exceed the threshold, then the throttling unit notifies the upstream computation unit to more restrictively throttle the thread by performing one or more of reducing the selection rate and increasing the time period. Otherwise, the unit notifies the upstream computation unit to less restrictively throttle the thread.

公开(公告)号：US20210073137A1

公开(公告)日：2021-03-11

申请号：US16562128

申请日：2019-09-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul James Moyer ,  Douglas Benson Hunt

IPC: G06F12/0891 ,  G06F9/38 ,  G06F12/0811 ,  G06F9/30

Abstract: Systems, apparatuses, and methods for generating a measurement of write memory bandwidth are disclosed. A control unit monitors writes to a cache hierarchy. If a write to a cache line is a first time that the cache line is being modified since entering the cache hierarchy, then the control unit increments a write memory bandwidth counter. Otherwise, if the write is to a cache line that has already been modified since entering the cache hierarchy, then the write memory bandwidth counter is not incremented. The first write to a cache line is a proxy for write memory bandwidth since this will eventually cause a write to memory. The control unit uses the value of the write memory bandwidth counter to generate a measurement of the write memory bandwidth. Also, the control unit can maintain multiple counters for different thread classes to calculate the write memory bandwidth per thread class.

公开(公告)号：US10366027B2

公开(公告)日：2019-07-30

申请号：US15826065

申请日：2017-11-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Eric Christopher Morton ,  Elizabeth Cooper ,  William L. Walker ,  Douglas Benson Hunt ,  Richard Martin Born ,  Richard H. Lee ,  Paul C. Miranda ,  Philip Ng ,  Paul Moyer

IPC: G06F13/28 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0891 ,  G06F12/0893

Abstract: A method for steering data for an I/O write operation includes, in response to receiving the I/O write operation, identifying, at an interconnect fabric, a cache of one of a plurality of compute complexes as a target cache for steering the data based on at least one of: a software-provided steering indicator, a steering configuration implemented at boot initialization, and coherency information for a cacheline associated with the data. The method further includes directing, via the interconnect fabric, the identified target cache to cache the data from the I/O write operation. The data is temporarily buffered at the interconnect fabric, and if the target cache attempts to fetch the data while the data is still buffered at the interconnect fabric, the interconnect fabric provides a copy of the buffered data in response to the fetch operation instead of initiating a memory access operation to obtain the data from memory.