公开(公告)号：US12050531B2

公开(公告)日：2024-07-30

申请号：US17952697

申请日：2022-09-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Kishore Punniyamurthy ,  Jagadish B Kotra

IPC: G06F12/02

CPC classification number: G06F12/0292 ,  G06F2212/1024 ,  G06F2212/401

Abstract: In accordance with the described techniques for data compression and decompression for processing in memory, a page address is received by a processing in memory component that maps to a first location in memory where data of a page is maintained. The data of the page is compressed by the processing in memory component. Further, compressed data of the page is written by the processing in memory component to a compressed block device responsive to the compressed data satisfying one or more compressibility criteria. The compressed block device is a portion of the memory dedicated to storing data in a compressed form.

公开(公告)号：US20240211399A1

公开(公告)日：2024-06-27

申请号：US18089480

申请日：2022-12-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Kishore Punniyamurthy ,  Khaled Hamidouche ,  Brandon Keith Potter

IPC: G06F12/0813 ,  G06N20/00

CPC classification number: G06F12/0813 ,  G06N20/00

Abstract: A distributed cache network used for machine learning is provided which comprises a network fabric having file systems which store data and a plurality of processing devices, each comprising cache memory and a processor configured to execute a training of a machine learning model and selectively cache portions of the data based on a frequency with which the data is accessed by the processor. Each processing device stores metadata identifying portions of data which are cached in the cache memory and other portions of the data which are cached in other processing devices of the network. When requested data is not cached in another processing device, the portion of requested data is accessed from a network file system via a client to server channel and is accessed from another processing device via a client to client channel when the requested data is cached in the other processing device.

公开(公告)号：US20240104015A1

公开(公告)日：2024-03-28

申请号：US17952697

申请日：2022-09-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Kishore Punniyamurthy ,  Jagadish B Kotra

IPC: G06F12/02

CPC classification number: G06F12/0292 ,  G06F2212/1024 ,  G06F2212/401

Abstract: In accordance with the described techniques for data compression and decompression for processing in memory, a page address is received by a processing in memory component that maps to a first location in memory where data of a page is maintained. The data of the page is compressed by the processing in memory component. Further, compressed data of the page is written by the processing in memory component to a compressed block device responsive to the compressed data satisfying one or more compressibility criteria. The compressed block device is a portion of the memory dedicated to storing data in a compressed form.

公开(公告)号：US20240005126A1

公开(公告)日：2024-01-04

申请号：US17853670

申请日：2022-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Kishore Punniyamurthy ,  Khaled Hamidouche ,  Brandon K. Potter ,  Rohit Shahaji Zambre

IPC: G06N3/04 ,  G06N3/08

CPC classification number: G06N3/04 ,  G06N3/08

Abstract: An electronic device includes one or more data producing nodes and a data consuming node. Each data producing node separately generates two or more portions of a respective block of data. Upon completing generating each portion of the two or more portions of the respective block of data, each data producing node communicates that portion of the respective block of data to the data consuming node. Upon receiving corresponding portions of the respective blocks of data from each of the one or more data producing nodes, the data consuming node performs operations for a model using the corresponding portions of the respective blocks of data.

公开(公告)号：US20230169015A1

公开(公告)日：2023-06-01

申请号：US17539189

申请日：2021-11-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Kishore Punniyamurthy ,  SeyedMohammad SeyedzadehDelcheh ,  Sergey Blagodurov ,  Ganesh Dasika ,  Jagadish B. Kotra

IPC: G06F12/126

CPC classification number: G06F12/126 ,  G06F2212/6042

Abstract: A method includes storing a function representing a set of data elements stored in a backing memory and, in response to a first memory read request for a first data element of the set of data elements, calculating a function result representing the first data element based on the function.

公开(公告)号：US20210173796A1

公开(公告)日：2021-06-10

申请号：US16706421

申请日：2019-12-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Sooraj Puthoor ,  Kishore Punniyamurthy ,  Onur Kayiran ,  Xianwei Zhang ,  Yasuko Eckert ,  Johnathan Alsop ,  Bradford Michael Beckmann

IPC: G06F13/18 ,  G06F13/16

Abstract: Systems, apparatuses, and methods for implementing memory request priority assignment techniques for parallel processors are disclosed. A system includes at least a parallel processor coupled to a memory subsystem, where the parallel processor includes at least a plurality of compute units for executing wavefronts in lock-step. The parallel processor assigns priorities to memory requests of wavefronts on a per-work-item basis by indexing into a first priority vector, with the index generated based on lane-specific information. If a given event is detected, a second priority vector is generated by applying a given priority promotion vector to the first priority vector. Then, for subsequent wavefronts, memory requests are assigned priorities by indexing into the second priority vector with lane-specific information. The use of priority vectors to assign priorities to memory requests helps to reduce the memory divergence problem experienced by different work-items of a wavefront.