公开(公告)号：US20180307622A1

公开(公告)日：2018-10-25

申请号：US15495707

申请日：2017-04-24

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Wade K. Smith ,  Anthony Asaro

IPC: G06F12/1045 ,  G06F12/1027 ,  G06F12/1009

CPC classification number: G06F12/1063 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/65 ,  G06F2212/68

Abstract: Systems, apparatuses, and methods for implementing a virtualized translation lookaside buffer (TLB) are disclosed herein. In one embodiment, a system includes at least an execution unit and a first TLB. The system supports the execution of a plurality of virtual machines in a virtualization environment. The system detects a translation request generated by a first virtual machine with a first virtual memory identifier (VMID). The translation request is conveyed from the execution unit to the first TLB. The first TLB performs a lookup of its cache using at least a portion of a first virtual address and the first VMID. If the lookup misses in the cache, the first TLB allocates an entry which is addressable by the first virtual address and the first VMID, and the first TLB sends the translation request with the first VMID to a second TLB.

公开(公告)号：US20180246816A1

公开(公告)日：2018-08-30

申请号：US15442487

申请日：2017-02-24

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Wade K. Smith ,  Kostantinos Danny Christidis

IPC: G06F12/1027 ,  G06F12/1081 ,  G06F12/1009 ,  G06F9/38

Abstract: Techniques are provided for using a translation lookaside buffer to provide low latency memory address translations for data streams. Clients of a memory system first prepare the address translation cache hierarchy by requesting that a translation pre-fetch stream is initialized. After the translation pre-fetch stream is initialized, the cache hierarchy returns an acknowledgment of completion to the client, which then begins to access memory. Pre-fetch streams are specified in terms of address ranges and are performed for large contiguous portions of the virtual memory address space.

公开(公告)号：US20180246815A1

公开(公告)日：2018-08-30

申请号：US15442462

申请日：2017-02-24

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Wade K. Smith ,  Kostantinos Danny Christidis

IPC: G06F12/1027 ,  G06F12/1081 ,  G06F12/1009 ,  G06F9/38

CPC classification number: G06F12/1027 ,  G06F9/3887 ,  G06F12/1009 ,  G06F12/1081 ,  G06F2212/681 ,  G06F2212/684

Abstract: Techniques are provided for managing address translation request traffic where memory access requests can be made with differing quality-of-service levels, which specify latency and/or bandwidth requirements. The techniques involve translation lookaside buffers. Within the translation lookaside buffers, certain resources are reserved for specific quality-of-service levels. More specifically, translation lookaside buffer slots, which store the actual translations, as well as finite state machines in a work queue, are reserved for specific quality-of-service levels. The translation lookaside buffer receives multiple requests for address translation. The translation lookaside buffer selects requests having the highest quality-of-service level for which an available finite state machine is available. The fact that finite state machines are reserved to particular quality-of-service levels means that if all such finite state machines for a particular quality-of-service level are used by pending translation requests, then the translation lookaside buffer does not accept more translation requests for that quality-of-service level.