公开(公告)号：US10079156B2

公开(公告)日：2018-09-18

申请号：US14703794

申请日：2015-05-04

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Chih-Cheng Lee ,  Yuan-Chang Su ,  Yu-Lin Shih ,  You-Lung Yen

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56

CPC classification number: H01L21/481 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/92144

Abstract: The present disclosure relates to a semiconductor package and method of making the same. The semiconductor package includes an encapsulation layer, a component within the encapsulation layer, a first dielectric layer, a second dielectric layer, a first patterned conductive layer, and a second patterned conductive layer. The component includes pads on a front surface of the component. The first dielectric layer is disposed on a surface of the encapsulation layer. The second dielectric layer is disposed on a surface of the first dielectric layer. The first and second dielectric layers define via holes extending from the second dielectric layer to respective ones of the pads. The first patterned conductive layer is disposed within the first dielectric layer and surrounds the via holes. The second patterned conductive layer is disposed within the second dielectric layer and surrounds the via holes.

公开(公告)号：US20160133537A1

公开(公告)日：2016-05-12

申请号：US14536253

申请日：2014-11-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Lin Shih ,  Chih-Cheng Lee

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/288 ,  H01L21/768 ,  H01L23/532 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L21/288 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76805 ,  H01L21/76838 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/83 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/838 ,  H01L2224/92144

Abstract: The present disclosure relates to a semiconductor package and method of making the same. The semiconductor package includes an encapsulation layer, a dielectric layer, a component, and a first patterned conductive layer. The encapsulation layer has a first surface. The component is within the encapsulation layer and has a front surface and a plurality of pads on the front surface. The dielectric layer is on the first surface of the encapsulation layer, and defines a plurality of via holes; wherein the plurality of pads of the component are against the dielectric layer; and wherein the dielectric layer has a second surface opposite the first surface of the encapsulation layer. Each of plurality of via holes extends from the second surface of the dielectric layer to a respective one of the plurality of the pads. The first patterned conductive layer is within the dielectric layer and surrounds the via holes.

Abstract translation: 本公开涉及一种半导体封装及其制造方法。 半导体封装包括封装层，电介质层，元件和第一图案化导电层。 封装层具有第一表面。 该组件在封装层内，并且在前表面上具有前表面和多个焊盘。 介电层位于封装层的第一表面上，并且限定多个通孔; 其中所述部件的所述多个焊盘抵靠所述电介质层; 并且其中所述电介质层具有与所述封装层的第一表面相对的第二表面。 多个通孔中的每一个从电介质层的第二表面延伸到多个焊盘中的相应一个。 第一图案化导电层在电介质层内并包围通孔。