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公开(公告)号：US20120278372A1
公开(公告)日：2012-11-01
申请号：US13494636
申请日：2012-06-12
申请人： Sergey Gribok , Alexander Andreev , Sergey Gashkov
发明人： Sergey Gribok , Alexander Andreev , Sergey Gashkov
CPC分类号： G06F7/588 , G06F7/724 , H04L9/0861
摘要： An apparatus and method are provided in various illustrative embodiments for an integrated circuit chip that provides a fast, compact, and cryptographically strong random number generator. In one illustrative embodiment, an apparatus includes an initial random source, and a post-processing block in communicative connection with the initial random source. The post-processing block is configured to receive signals from the initial random source, to apply one or more finite field operations to the signals to generate an output, and to provide an output signal based on the output via an output channel, in this illustrative embodiment.
摘要翻译： 在提供快速，紧凑和密码强的随机数发生器的集成电路芯片的各种说明性实施例中提供了一种装置和方法。 在一个说明性实施例中，装置包括初始随机源和与初始随机源通信连接的后处理块。 后处理块被配置为从初始随机源接收信号，以将一个或多个有限场操作施加到信号以产生输出，并且在该说明性视图中通过输出通道提供基于输出的输出信号 实施例。
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公开(公告)号：US07913149B2
公开(公告)日：2011-03-22
申请号：US11613256
申请日：2006-12-20
IPC分类号： H03M13/00
CPC分类号： H03M13/116 , H03M13/1185
摘要： A method of encoding a binary source message u, by calculating x:=Au, calculating y:=B′x, resolving the equation Dp=y for p, and incorporating u and p to produce an encoded binary message v, where A is a matrix formed only of permutation sub matrices, B′ is a matrix formed only of circulant permutation sub matrices, and D is a matrix of the form D = ( T 0 … 0 0 0 T … 0 0 … … … … … 0 0 … T 0 I I … I I ) where T is a two-diagonal, circulant sub matrix, and I is an identity sub matrix.
摘要翻译： 通过计算x：= Au来计算二进制源消息u，计算y：= B'x，解析p的等式Dp = y，并且并入u和p以产生编码的二进制消息v，其中A是 一个仅由置换子矩阵构成的矩阵，B'是仅由循环置换子矩阵形成的矩阵，D是形式为D =（T 0 ... 0 0 0 T ... 0 0 ...... ...... 0 0 ... T 0 II ... II）其中T是双对角，循环子矩阵，I是身份子矩阵。
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公开(公告)号：US20080168334A1
公开(公告)日：2008-07-10
申请号：US11613256
申请日：2006-12-20
CPC分类号： H03M13/116 , H03M13/1185
摘要： A method of encoding a binary source message u, by calculating x:=Au, calculating y:=B″x, resolving the equation Dp=y for p, and incorporating u and p to produce an encoded binary message v, where A is a matrix formed only of permutation sub matrices, B′ is a matrix formed only of circulant permutation sub matrices, and D is a matrix of the form D = ( T 0 ⋯ 0 0 0 T ⋯ 0 0 ⋯ ⋯ ⋯ ⋯ ⋯ 0 0 ⋯ T 0 I I ⋯ I I ) where T is a two-diagonal, circulant sub matrix, and I is an identity sub matrix.
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公开(公告)号：US20110173510A1
公开(公告)日：2011-07-14
申请号：US13069105
申请日：2011-03-22
CPC分类号： H03M13/116 , H03M13/1137 , H03M13/114
摘要： An LDPC decoder that implements an iterative message-passing algorithm, where the improvement includes a pipeline architecture such that the decoder accumulates results for row operations during column operations, such that additional time and memory are not required to store results from the row operations beyond that required for the column operations.
摘要翻译： 实现迭代消息传递算法的LDPC解码器，其中改进包括流水线架构，使得解码器在列操作期间累积行操作的结果，使得不需要额外的时间和存储器来存储超过该操作的行操作的结果 列操作需要。
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公开(公告)号：US20100030835A1
公开(公告)日：2010-02-04
申请号：US12185404
申请日：2008-08-04
申请人： Alexander Andreev , Sergey Gribok , Oleg Izyumin
发明人： Alexander Andreev , Sergey Gribok , Oleg Izyumin
IPC分类号： G06F11/00
CPC分类号： G06F7/575 , H03M13/1102 , H03M13/1111 , H03M13/1117
摘要： A variable node processing unit with N+1 inputs, having at least a first bank of two-input adders and a separate last bank of two-input adders, where the banks of adders are disposed in series.
摘要翻译： 具有N + 1个输入的可变节点处理单元，其具有至少第一组双输入加法器和独立的最后一组双输入加法器，其中加法器组串联配置。
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公开(公告)号：US20090287980A1
公开(公告)日：2009-11-19
申请号：US12121824
申请日：2008-05-16
申请人： Sergey Gribok , Alexander Andreev
发明人： Sergey Gribok , Alexander Andreev
CPC分类号： H04L1/0052 , G06F11/1008 , G06F15/7867
摘要： A device for soft decoding contains a set of operational elements, each being capable of performing one of several different functions. The operational elements may be dynamically configured with input and output connections to registers, memory locations, and other operational elements to perform various steps in a soft decoding scheme. In many cases, the operational elements may be configured to operate in a pipeline mode where many sequences of operations may be performed in parallel. Some embodiments may be reconfigured at each clock cycle to perform different steps during a decoding operation. The device may be used to perform several different soft decoding schemes with the flexibility of a programmable processor but the throughput of a hardware implementation.
摘要翻译： 用于软解码的设备包含一组操作元件，每个操作元件能够执行若干不同功能之一。 操作元件可以被动态配置为具有到寄存器，存储器位置和其他操作元件的输入和输出连接，以在软解码方案中执行各种步骤。 在许多情况下，操作元件可以被配置为在可以并行执行许多操作序列的流水线模式下操作。 可以在每个时钟周期重新配置一些实施例，以在解码操作期间执行不同的步骤。 该设备可以用于执行具有可编程处理器的灵活性但是硬件实现的吞吐量的几种不同的软解码方案。
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公开(公告)号：US20080134008A1
公开(公告)日：2008-06-05
申请号：US11565670
申请日：2006-12-01
CPC分类号： H03M13/116 , H03M13/1137 , H03M13/114
摘要： An LDPC decoder that implements an iterative message-passing algorithm, where the improvement includes a pipeline architecture such that the decoder accumulates results for row operations during column operations, such that additional time and memory are not required to store results from the row operations beyond that required for the column operations.
摘要翻译： 实现迭代消息传递算法的LDPC解码器，其中改进包括流水线架构，使得解码器在列操作期间累积行操作的结果，使得不需要额外的时间和存储器来存储超过该操作的行操作的结果 列操作需要。
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公开(公告)号：US20060161803A1
公开(公告)日：2006-07-20
申请号：US11038698
申请日：2005-01-20
IPC分类号： G06F11/00
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/72
摘要： The present invention provides a memory BISR architecture for a slice. The architecture includes (1) a plurality of physical memory instances; (2) a Mem_BIST controller, communicatively coupled to the plurality of physical memory instances, for testing the plurality of physical memory instances; (3) a FLARE module, communicatively coupled to the Mem_BIST controller, including a scan chain of registers for storing test results of the plurality of physical memory instances, each of the plurality of physical memory instances M_i being assigned one FLARE bit f_i, i=1, 2, . . . , n, the FLARE module being used by the Mem_BIST controller to scan in an error vector F=(f—1, f—2, . . . , f_n); (4) a BISR controller, communicatively coupled to the FLARE module, a ROM module and a REPAIR_CONFIGURATION module, for scanning out the error vector F from the FLARE module to computer a repair configuration vector R=(r—1, r—2, . . . , r_n); and (5) a FUSE module, communicatively coupled to the BISR controller and the REPAIR_CONFIGURATION module, for storing the repair configuration vector R. The REPAIR_CONFIGURATION module, communicatively coupled to the plurality of physical memory instances M_i and an integrated circuit design D, includes switch module instances S for switching among the plurality of physical memory instances in accordance with the repair configuration vector R. The ROM module stores a vector U indicating usage of the plurality of physical memory instances M_i by the integrated circuit design D.
摘要翻译： 本发明提供了一种用于切片的存储器BISR架构。 该架构包括（1）多个物理存储器实例; （2）通信地耦合到所述多个物理存储器实例的用于测试所述多个物理存储器实例的Mem_BIST控制器; （3）FLARE模块，通信地耦合到所述Mem_BIST控制器，包括用于存储所述多个物理存储器实例的测试结果的寄存器扫描链，所述多个物理存储器实例M_i中的每一个被分配一个FLARE位f_i，i = 1，2，... 。 。 ，n，由Mem_BIST控制器使用的FLARE模块以错误向量F =（f 1 - 1，f 2 - ，...，f_n）进行扫描; （4）通信地耦合到FLARE模块的BISR控制器，ROM模块和REPAIR_CONFIGURATION模块，用于从FLARE模块向计算机扫描出错误向量F，修复配置向量R =（r - > 1，r 2，...，r_n）; 和（5）通信地耦合到BISR控制器和REPAIR_CONFIGURATION模块的FUSE模块，用于存储修复配置向量R.通信地耦合到多个物理存储器实例M_i和集成电路设计D的REPAIR_CONFIGURATION模块包括开关 模块实例S，用于根据修复配置向量R在多个物理存储器实例之间切换.ROM模块通过集成电路设计D存储指示多个物理存储器实例M_i的使用的向量U。
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公开(公告)号：US20080320066A1
公开(公告)日：2008-12-25
申请号：US11821212
申请日：2007-06-22
申请人： Sergey Gribok , Alexander Andreev
发明人： Sergey Gribok , Alexander Andreev
CPC分类号： G06F7/588 , G06F7/724 , H04L9/0861
摘要： An apparatus and method are provided in various illustrative embodiments for an integrated circuit chip that provides a fast, compact, and cryptographically strong random number generator. In one illustrative embodiment, an apparatus includes an initial random source, and a post-processing block in communicative connection with the initial random source. The post-processing block is configured to receive signals from the initial random source, to apply one or more finite field operations to the signals to generate an output, and to provide an output signal based on the output via an output channel, in this illustrative embodiment.
摘要翻译： 在提供快速，紧凑和密码强的随机数发生器的集成电路芯片的各种说明性实施例中提供了一种装置和方法。 在一个说明性实施例中，装置包括初始随机源和与初始随机源通信连接的后处理块。 后处理块被配置为从初始随机源接收信号，以将一个或多个有限场操作应用于信号以产生输出，并且在该说明性视图中通过输出通道提供基于输出的输出信号 实施例。
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公开(公告)号：US20080109688A1
公开(公告)日：2008-05-08
申请号：US11557513
申请日：2006-11-08
申请人： Sergey Gribok , Alexander Andreev , Ivan Pavisic
发明人： Sergey Gribok , Alexander Andreev , Ivan Pavisic
IPC分类号： G11C29/00
CPC分类号： G11C29/16 , G11C29/34 , G11C2029/0401 , G11C2029/1204 , G11C2029/2602
摘要： A built in self test circuit disposed within a memory matrix. Individual memory cells within the memory matrix are disposed into logical columns. The built in self test circuit has only one memory test controller, which is adapted to initiate test commands and receive test results. Transport controllers are uniquely paired with each one of the logical columns of memory cells. Each of the transport controllers is adapted to receive test commands from the memory test controller, test memory cells within the logical column as instructed by the test commands, receive test results from the logical column of memory cells, and provide the test results to the memory test controller. The transport controllers are also adapted to selectively operate in three different modes under control of the memory test controller. A first production testing mode simultaneously tests the memory cells in different logical columns, while accumulating the test results for a given logical column with the transport controller associated with the given logical column. A second production testing mode retrieves the accumulated test results from the transport controllers. A diagnostic testing mode tests memory cells within one selected logical column, while simultaneously retrieving the test results for the one selected logical column.
摘要翻译： 设置在存储器矩阵内的内置自测电路。 存储器矩阵内的单个存储单元被放置在逻辑列中。 内置自检电路只有一个内存测试控制器，适用于启动测试命令并接收测试结果。 传输控制器与每个存储单元的逻辑列唯一配对。 每个传输控制器适于从存储器测试控制器接收测试命令，根据测试命令指示在逻辑列中测试存储器单元，从存储器单元的逻辑列接收测试结果，并将测试结果提供给存储器 测试控制器 传输控制器还适于在存储器测试控制器的控制下以三种不同的模式选择性地操作。 第一个生产测试模式同时测试不同逻辑列中的存储单元，同时使用与给定逻辑列相关联的传输控制器累积给定逻辑列的测试结果。 第二个生产测试模式从运输控制器检索累积的测试结果。 诊断测试模式测试一个所选逻辑列内的存储单元，同时检索所选逻辑列的测试结果。
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