公开(公告)号：US08004876B2

公开(公告)日：2011-08-23

申请号：US10233232

申请日：2002-08-30

申请人： Gregory S. Snider ,  Philip J. Kuekes ,  R. Stanley Williams

发明人： Gregory S. Snider ,  Philip J. Kuekes ,  R. Stanley Williams

IPC分类号： G11C11/00

CPC分类号： H01L27/285 ,  B82Y10/00 ,  G11C13/0009 ,  G11C13/0014 ,  G11C2213/14 ,  G11C2213/34 ,  G11C2213/77 ,  G11C2213/81

摘要： A computing system for implementing at least one electronic circuit with gain comprises at least one two-dimensional molecular switch array. The molecular switch array is formed by assembling two or more crossed planes of wires into a configuration of devices. Each device comprises a junction formed by a pair of crossed wires and at least one connector species that connects the pair of crossed wires in the junction. The junction has a functional dimension in nanometers, and includes a switching capability provided by both (1) one or more connector species and the pair of crossed wires and (2) a configurable nano-scale wire transistor having a first state that functions as a transistor and a second state that functions as a conducting semiconductor wire. Specific connections are made to interconnect the devices and connect the devices to two structures that provide high and low voltages.

摘要翻译： 用于实现具有增益的至少一个电子电路的计算系统包括至少一个二维分子开关阵列。 分子开关阵列通过将两个或更多个交叉的导线平面组装成器件的配置而形成。 每个装置包括由一对交叉线形成的连接点和连接该连接处的一对交叉线的至少一个连接器种类。 该结具有纳米的功能尺寸，并且包括由（1）一个或多个连接器种类和一对交叉导线提供的切换能力，以及（2）具有第一状态的可配置纳米级线晶体管，其具有作为 晶体管和作为导电半导体线的第二状态。 进行具体的连接来连接设备并将设备连接到提供高和低电压的两个结构。

公开(公告)号：US08812418B2

公开(公告)日：2014-08-19

申请号：US13256246

申请日：2009-06-22

申请人： Gregory S. Snider

发明人： Gregory S. Snider

IPC分类号： G06N3/063 ,  G06N3/04

CPC分类号： G06N3/063

摘要： A method for implementing an artificial neural network includes connecting a plurality of receiving neurons to a plurality of transmitting neurons through memristive synapses. Each memristive synapse has a weight which is initialized into a conductive state. A binary input vector is presented through the memristive synapses to the plurality of receiving neurons and the state of one or more of the memristive synapses modified based on the binary input vector.

摘要翻译： 一种用于实现人造神经网络的方法包括通过忆阻突触将多个接收神经元连接到多个发射神经元。 每个忆阻突触的重量都被初始化为导电状态。 通过对多个接收神经元的忆阻突触呈现二进制输入向量，并且基于二进制输入向量修改的一个或多个忆阻突触的状态。

公开(公告)号：US08166860B2

公开(公告)日：2012-05-01

申请号：US12848427

申请日：2010-08-02

申请人： Louis Gibbons ,  Gregory S. Snider ,  Frederick R. Bean ,  Terry L. Turner ,  Steven McClaskey ,  Robert H. Gifford

发明人： Louis Gibbons ,  Gregory S. Snider ,  Frederick R. Bean ,  Terry L. Turner ,  Steven McClaskey ,  Robert H. Gifford

IPC分类号： B23D45/14 ,  B23D45/04 ,  B23D47/04

CPC分类号： B27B27/08 ,  B23D45/042 ,  B27B5/29 ,  B27B27/10 ,  B27G5/023 ,  Y10T83/762 ,  Y10T83/7705 ,  Y10T83/773 ,  Y10T83/865

摘要： The present invention is directed toward a system for forming miter joints including a miter saw and an angle gauge. The miter saw includes a platform with a kerf slot and a pair of arcuate slots. Each arcuate slot includes an associated rail located on the underside of the platform. A fence is coupled to each of the rails such that the fence may be pivoted with respect to the platform. The angle measurement tool is a one-handed tool including spring loaded paddles that measure the angle between intersecting surfaces. The angle measurement tool connects to the miter saw to permit the transfer of the measured angle to the fences.

摘要翻译： 本发明涉及一种用于形成包括斜切锯和角度计的斜接头的系统。 斜切锯包括具有切口槽和一对弓形槽的平台。 每个弧形槽包括位于平台下侧的相关导轨。 栅栏连接到每个轨道，使得围栏可以相对于平台枢转。 角度测量工具是一个单手工具，包括弹簧加载桨叶，用于测量相交表面之间的角度。 角度测量工具连接到斜切锯，以允许将测量的角度传递到围栏。

公开(公告)号：US20120016829A1

公开(公告)日：2012-01-19

申请号：US13256246

申请日：2009-06-22

申请人： Gregory S. Snider

发明人： Gregory S. Snider

IPC分类号： G06N3/063 ,  G06N3/04

CPC分类号： G06N3/063

摘要： A method for implementing an artificial neural network includes connecting a plurality of receiving neurons to a plurality of transmitting neurons through memristive synapses (705). Each memristive synapse has a weight which is initialized into a conductive state (715). A binary input vector is presented through the memristive synapses to the plurality of receiving neurons (735) and the state of one or more of the memristive synapses modified based on the binary input vector (760).

摘要翻译： 实现人造神经网络的方法包括通过忆阻突触将多个接收神经元连接到多个发射神经元（705）。 每个忆阻突触具有初始化为导电状态的重量（715）。 通过对多个接收神经元（735）的忆阻突触呈现二进制输入向量，并且基于二进制输入向量（760）修改的一个或多个忆阻突触的状态。

公开(公告)号：US07720377B2

公开(公告)日：2010-05-18

申请号：US11337328

申请日：2006-01-23

申请人： Gregory S. Snider ,  Raymond Beausoleil

发明人： Gregory S. Snider ,  Raymond Beausoleil

IPC分类号： H04J14/00

CPC分类号： H04Q11/0001 ,  B82Y10/00 ,  B82Y20/00 ,  G02B6/1225 ,  G02B6/43 ,  G06N99/002 ,  H04B10/801 ,  H04L49/101 ,  H04L49/254 ,  H04L49/3045 ,  H04L49/357

摘要： Various embodiments of the present invention are directed to photonic-interconnection-based compute clusters that provide high-speed, high-bandwidth interconnections between compute cluster nodes. In one embodiment of the present invention, the compute cluster includes a photonic interconnection having one or more optical transmission paths for transmitting independent frequency channels within an optical signal to each node in a set of nodes. The compute cluster includes one or more photonic-interconnection-based writers, each writer associated with a particular node, and each writer encoding information generated by the node into one of the independent frequency channels. A switch fabric directs the information encoded in the independent frequency channels to one or more nodes in the compute cluster. The compute cluster also includes one or more photonic-interconnection-based readers, each reader associated with a particular node, and each reader extracting the information encoded in the independent frequency channels directed to the node for processing.

摘要翻译： 本发明的各种实施例涉及在计算集群节点之间提供高速，高带宽互连的基于光子互连的计算集群。 在本发明的一个实施例中，计算集群包括具有一个或多个光传输路径的光子互连，用于将光信号内的独立频率信道传送到一组节点中的每个节点。 计算集群包括一个或多个基于光子互连的写入器，每个写入器与特定节点相关联，并且每个写入器将由节点生成的信息编码为独立频率信道之一。 交换结构将在独立频率信道中编码的信息定向到计算集群中的一个或多个节点。 计算集群还包括一个或多个基于光子互连的读取器，每个读取器与特定节点相关联，并且每个读取器提取在指向节点的独立频率信道中编码的信息进行处理。

公开(公告)号：US07652911B2

公开(公告)日：2010-01-26

申请号：US12331642

申请日：2008-12-10

申请人： Gregory S. Snider ,  Philip J. Kuekes

发明人： Gregory S. Snider ,  Philip J. Kuekes

IPC分类号： G11C11/00

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C13/0023 ,  G11C19/00 ,  G11C2213/17 ,  G11C2213/77 ,  G11C2213/81

摘要： Methods for inputting a data-value pattern into a nanowire crossbar, for inputting a data-value pattern into a nanowire crossbar that support computer instructions stored in a computer-readable medium, and for distributing a received data value to each of a set of nanowires that support control logic implemented in logic circuits are provided. First and second nanoscale shift registers are employed, the first having output signal lines that form or interconnect with a first parallel set of nanowire-crossbar nanowires and the second having output signal lines that form or interconnect with a second parallel set of nanowire-crossbar nanowires. A first pattern of values is stored in the first shift register and a second pattern of values is stored in the second shift register using voltage signals below the WRITE voltage for junctions of the crossbar. Voltage signals greater than or equal to the WRITE threshold are applied for junctions of the crossbar to write the pattern of data values into the crossbar.

摘要翻译： 用于将数据值图案输入到纳米线交叉开关中的方法，用于将数据值图案输入到支持存储在计算机可读介质中的计算机指令的纳米线交叉开关中，以及用于将接收到的数据值分配到一组纳米线中的每一个 提供了在逻辑电路中实现的支持控制逻辑。 采用第一和第二纳米级移位寄存器，第一和第二纳米尺度移位寄存器，其中第一和第二纳米尺度移位寄存器，其中第一和第二纳米尺度移位寄存器，其中第一和第二纳米尺度移位寄存器，其中第一和第二纳米尺度的移动寄存器， 。 值的第一模式被存储在第一移位寄存器中，并且第二模式的值被存储在第二移位寄存器中，该电压信号低于用于交叉开关的接点的写电压。 施加大于或等于WRITE阈值的电压信号用于交叉开关的交叉点，以将数据值的模式写入交叉开关。

公开(公告)号：US07444495B1

公开(公告)日：2008-10-28

申请号：US10232970

申请日：2002-08-30

申请人： Gregory S. Snider

发明人： Gregory S. Snider

IPC分类号： G06F9/455 ,  G06F15/163

CPC分类号： G06F9/30174 ,  G06F9/45504

摘要： A computing arrangement including a processor and programmable logic. In various embodiments, the arrangement includes an instruction processing circuit coupled to a programmable logic circuit, and a memory arrangement coupled to the instruction processing circuit and to the programmable logic circuit. The instruction processing circuit executes instructions of a native instruction set, and the programmable logic is configured to dynamically translate input instructions to translated instructions of the native instruction set. The translated instructions are stored in a translation cache in the memory arrangement, and the translation cache is managed by the programmable logic. The programmable logic then provides the translated instructions to the instruction processing circuit for execution.

摘要翻译： 一种包括处理器和可编程逻辑的计算装置。 在各种实施例中，该装置包括耦合到可编程逻辑电路的指令处理电路和耦合到指令处理电路和可编程逻辑电路的存储器装置。 指令处理电路执行本地指令集的指令，并且可编程逻辑被配置为将输入指令动态地转换为本地指令集的转换指令。 翻译的指令被存储在存储器装置中的转换高速缓存中，并且转换高速缓存由可编程逻辑管理。 然后，可编程逻辑将转换的指令提供给指令处理电路以供执行。

公开(公告)号：US07436209B1

公开(公告)日：2008-10-14

申请号：US11590491

申请日：2006-10-30

申请人： Gregory S. Snider ,  Philip J. Kuekes

发明人： Gregory S. Snider ,  Philip J. Kuekes

IPC分类号： H03K19/177

CPC分类号： H01L27/10 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673

摘要： In one embodiment of the present invention, a nanoscale latch is implemented by interconnecting an enable line, two control lines, and a pull-down line, when needed, to a signal line carrying encoded binary values to be latched and subsequently output. The enable line is interconnected with the signal line through a field-effect-transistor-like nanoscale junction. Both control lines are interconnected with the signal line through asymmetric-switch nanoscale junctions of like polarities. The pull-down line, when needed, is interconnected with the signal line through a resistive nanoscale junction. Inputting a sequence of signals to the enable and control lines allows a value input from the signal line to be stored and subsequently output to the signal line. In various additional embodiments, an array of nanoscale latches can be implemented by overlaying enable and control lines, and a pull-down line when needed, over a set of parallel nanowires.

摘要翻译： 在本发明的一个实施例中，纳米尺度锁存器通过在需要时将使能线，两条控制线和下拉线互连到一个承载要锁存并随后输出的编码二进制值的信号线来实现。 使能线通过场效应晶体管状纳米级结与信号线互连。 两个控制线通过具有相似极性的非对称开关纳米级结与信号线互连。 当需要时，下拉线通过电阻性纳米级结与信号线互连。 将一系列信号输入到使能和控制线路允许从信号线输入的值被存储并随后输出到信号线。 在各种附加实施例中，纳米尺度锁存器的阵列可以通过在一组平行纳米线上覆盖使能和控制线以及需要时的下拉线来实现。

公开(公告)号：USD573459S1

公开(公告)日：2008-07-22

申请号：US29278255

申请日：2007-03-23

申请人： Gregory S. Snider ,  Marc Salois

设计人： Gregory S. Snider ,  Marc Salois

公开(公告)号：US07319416B2

公开(公告)日：2008-01-15

申请号：US11343325

申请日：2006-01-30

申请人： Warren Robinett ,  Gregory S. Snider ,  Duncan Stewart ,  Joseph Straznicky

发明人： Warren Robinett ,  Gregory S. Snider ,  Duncan Stewart ,  Joseph Straznicky

IPC分类号： H03M7/14

CPC分类号： G11C8/10 ,  G11C13/0023 ,  H03M13/51

摘要： Various embodiments of the present invention are directed to demultiplexers that include tunneling resistor nanowire junctions, and to nanowire addressing methods for reliably addressing nanowire signal lines in nanoscale and mixed-scale demultiplexers. In one embodiment of the present invention, an encoder-demultiplexer comprises a number of input signal lines and an encoder that generates an n-bit-constant-weight-code code-word internal address for each different input address received on the input signal lines. The encoder-demultiplexer includes n microscale signal lines on which an n-bit-constant-weight-code code-word internal address is output by the encoder, where each microscale signal line carries one bit of the n-bit-constant-weight-code code-word internal address. The encoder-demultiplexer also includes a number of encoder-demultiplexer-addressed nanowire signal lines interconnected with the n microscale signal lines via tunneling resistor junctions, the encoder-demultiplexer-addressed nanowire signal lines each associated with an n-bit-constant-weight-code code-word internal address.

摘要翻译： 本发明的各种实施例涉及包括隧穿电阻器纳米线结的解复用器，以及纳米线寻址方法，用于在纳米尺度和混合尺度解复用器中可靠地寻址纳米线信号线。 在本发明的一个实施例中，编码器 - 解复用器包括多个输入信号线和一个编码器，其生成在输入信号线上接收的每个不同输入地址的n位恒权重码码字内部地址 。 编码器 - 解复用器包括n个微米级信号线，编码器输出n位恒定权重码码字内部地址，其中每个微信号线承载n位恒权重码内部地址的一位， 代码字内部地址。 编码器 - 解复用器还包括通过隧道电阻器结与n个微米级信号线互连的多个编码器 - 解复用器寻址的纳米线信号线，编码器 - 解复用器寻址的纳米线信号线每个与n比特恒权重信号线相关联， 代码字内部地址。