公开(公告)号：US11195826B2

公开(公告)日：2021-12-07

申请号：US16776680

申请日：2020-01-30

Applicant: Allegro MicroSystems, LLC

Inventor： Maxim Klebanov ,  Washington Lamar ,  Sagar Saxena ,  Chung C. Kuo ,  Sebastian Courtney ,  Sundar Chetlur

IPC: H01L27/02 ,  H02H9/04 ,  H01L29/866

Abstract: In one aspect an electronic device includes a substrate having one of a p-type doping or an n-type doping, a first well in the substrate, a second well in the substrate, a third well in the substrate between the first and second wells, a first terminal connected to the first well, a second terminal connected to the second well, an electrostatic discharge (ESD) clamp connected to the first and second terminals and a transient voltage source connected to the third well. A doping type of the first, second and third wells is the other one of the p-type or n-type doping. The ESD clamp is configured to clamp the first and second wells at a clamp voltage during an ESD event and the transient voltage source is configured to provide a voltage during the ESD event that is less than the clamp voltage.

公开(公告)号：US20210242193A1

公开(公告)日：2021-08-05

申请号：US16776680

申请日：2020-01-30

Applicant: Allegro MicroSystems, LLC

Inventor： Maxim Klebanov ,  Washington Lamar ,  Sagar Saxena ,  Chung C. Kuo ,  Sebastian Courtney ,  Sundar Chetlur

IPC: H01L27/02 ,  H02H9/04 ,  H01L29/866

Abstract: In one aspect an electronic device includes a substrate having one of a p-type doping or an n-type doping, a first well in the substrate, a second well in the substrate, a third well in the substrate between the first and second wells, a first terminal connected to the first well, a second terminal connected to the second well, an electrostatic discharge (ESD) clamp connected to the first and second terminals and a transient voltage source connected to the third well. A doping type of the first, second and third wells is the other one of the p-type or n-type doping. The ESD clamp is configured to clamp the first and second wells at a clamp voltage during an ESD event and the transient voltage source is configured to provide a voltage during the ESD event that is less than the clamp voltage.

公开(公告)号：US20170287894A1

公开(公告)日：2017-10-05

申请号：US15089787

申请日：2016-04-04

Applicant: Allegro Microsystems, LLC

Inventor： Chung C. Kuo ,  Maxim Klebanov

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/739 ,  H01L29/10 ,  H01L29/78 ,  H01L29/866

CPC classification number: H01L27/0259 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/0266 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7393 ,  H01L29/7412 ,  H01L29/7436 ,  H01L29/7821 ,  H01L29/861 ,  H01L29/866 ,  H01L29/87

Abstract: In one aspect, a silicon-controlled rectifier (SCR) includes a Zener diode embedded in the SCR. In another aspect, a laterally diffused metal oxide semiconductor (LDMOS) includes a Zener diode embedded in the LDMOS. In a further aspect, a lateral insulated-gate bipolar transistor (IGBT) includes a Zener diode embedded in the IGBT.