公开(公告)号：US20240063310A1

公开(公告)日：2024-02-22

申请号：US17819957

申请日：2022-08-16

Applicant: Allegro MicroSystems, LLC

Inventor： Yu-Chun Li ,  Felix Palumbo ,  Chung C. Kuo ,  Thomas S. Chung ,  Maxim Klebanov

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/872 ,  H01L29/0623 ,  H01L29/402

Abstract: A Schottky diode includes a substrate having a first type dopant, a buried layer within the substrate and having a second type dopant, an epitaxial layer above the buried layer and having the second type dopant, a plurality of rings within the epitaxial layer and having the first type dopant, wherein the plurality of rings comprises an L-shaped ring, a shallow trench isolation (STI) layer at the top region of the epitaxial layer, an anode, a cathode spaced from the anode by the STI layer, and wherein the buried layer has an open region substantially vertically aligned with the anode.

公开(公告)号：US12119413B2

公开(公告)日：2024-10-15

申请号：US17819957

申请日：2022-08-16

Applicant: Allegro MicroSystems, LLC

Inventor： Yu-Chun Li ,  Felix Palumbo ,  Chung C. Kuo ,  Thomas S. Chung ,  Maxim Klebanov

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/872 ,  H01L29/0623 ,  H01L29/402

Abstract: A Schottky diode includes a substrate having a first type dopant, a buried layer within the substrate and having a second type dopant, an epitaxial layer above the buried layer and having the second type dopant, a plurality of rings within the epitaxial layer and having the first type dopant, wherein the plurality of rings comprises an L-shaped ring, a shallow trench isolation (STI) layer at the top region of the epitaxial layer, an anode, a cathode spaced from the anode by the STI layer, and wherein the buried layer has an open region substantially vertically aligned with the anode.

公开(公告)号：US11967650B2

公开(公告)日：2024-04-23

申请号：US17662101

申请日：2022-05-05

Applicant: Allegro MicroSystems, LLC

Inventor： Sagar Saxena ,  Washington Lamar ,  Maxim Klebanov ,  Chung C. Kuo ,  Sebastian Courtney ,  Sundar Chetlur

IPC: H01L29/87 ,  H01L29/06

CPC classification number: H01L29/87 ,  H01L29/0684

Abstract: In one aspect, a diode includes a substrate having a first type dopant; a buried layer having a second type dopant and formed within the substrate; an epitaxial layer having the second type dopant and formed above the buried layer; and a plurality of regions having the first type dopant within the epitaxial layer. The plurality of regions includes a first region, a second region, and a third region. The diode also includes a base well having the first type dopant and located within the epitaxial layer and in contact with the third and fourth regions. In a reverse-bias mode, the diode is an electrostatic discharge (ESD) clamp and forms parasitic transistors comprising a first bipolar junction transistor (BJT), a second BJT and a third BJT.

公开(公告)号：US10056364B1

公开(公告)日：2018-08-21

申请号：US15481882

申请日：2017-04-07

Applicant: Allegro MicroSystems, LLC

Inventor： Maxim Klebanov ,  Washington Lamar ,  Richard B. Cooper ,  Chung C. Kuo

IPC: H01L29/66 ,  H01L27/02 ,  H01L29/40 ,  H01L29/866 ,  H01L29/739

CPC classification number: H01L27/0255 ,  H01L29/402 ,  H01L29/866

Abstract: An electrical device may include a substrate; a first doped region of the substrate having a p doping type; a second doped region adjacent to the first doped region of the substrate having an n doping type, wherein an interface between the first and second doped regions forms a p-n junction; and a circuit element placed in spaced relation to the p-n junction, the circuit element configured to produce an electric field that interacts with the p-n junction to change a reverse breakdown voltage of the p-n junction. Applicants for the electrical device include ESD protection circuits.

公开(公告)号：US20240405124A1

公开(公告)日：2024-12-05

申请号：US18327200

申请日：2023-06-01

Applicant: Allegro MicroSystems, LLC

Inventor： Yu-Chun Li ,  Thomas S. Chung ,  Maxim Klebanov ,  Chung C. Kuo ,  James M. McClay ,  Robert A. Wilson

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

Abstract: According to one aspect of the present disclosure, a semiconductor device includes a substrate having a first type dopant. In some embodiments, the semiconductor device also includes an epitaxial layer above the substrate, having a second type dopant and a top region. In some embodiments, the semiconductor device also includes a trench in the top region of the epitaxial layer; at least one doped ring implanted in the epitaxial layer below the trench; and a dielectric material filling within the trench. In some embodiments, there is a twelve-sided body tie in the epitaxial layer, wherein the sides of the twelve-sided body tie are not all equal to each other.

公开(公告)号：US20240170478A1

公开(公告)日：2024-05-23

申请号：US18058318

申请日：2022-11-23

Applicant: Allegro MicroSystems, LLC

Inventor： Chung C. Kuo ,  Maxim Klebanov ,  James McClay ,  Sagar Saxena

IPC: H01L27/02

CPC classification number: H01L27/0274

Abstract: In one aspect, a semiconductor device includes a first region, a second region and a trench separating the first and the second regions. The trench includes a trench liner that includes a dielectric, and a semiconductor material surrounded by the trench liner. The first region includes a first buried layer implanted in a substrate, a first stack of layers that includes a first middle layer located above the first buried layer, a first well located on and in contact with the first middle layer and a second well in contact with the first well. The second region includes a second stack of layers. In response to a voltage difference between the first and the second regions exceeding a threshold voltage, a conduction current is formed. A distance of the first stack of layers to the trench controls the conduction current to activate a transistor to function as a voltage clamp.

公开(公告)号：US20230361223A1

公开(公告)日：2023-11-09

申请号：US17662101

申请日：2022-05-05

Applicant: Allegro MicroSystems, LLC

Inventor： Sagar Saxena ,  Washington Lamar ,  Maxim Klebanov ,  Chung C. Kuo ,  Sebastian Courtney ,  Sundar Chetlur

IPC: H01L29/87 ,  H01L29/06

CPC classification number: H01L29/87 ,  H01L29/0684

Abstract: In one aspect, a diode includes a substrate having a first type dopant; a buried layer having a second type dopant and formed within the substrate; an epitaxial layer having the second type dopant and formed above the buried layer; and a plurality of regions having the first type dopant within the epitaxial layer. The plurality of regions includes a first region, a second region, and a third region. The diode also includes a base well having the first type dopant and located within the epitaxial layer and in contact with the third and fourth regions. In a reverse-bias mode, the diode is an electrostatic discharge (ESD) clamp and forms parasitic transistors comprising a first bipolar junction transistor (BJT), a second BJT and a third BJT.

公开(公告)号：US09929141B2

公开(公告)日：2018-03-27

申请号：US15089787

申请日：2016-04-04

Applicant: Allegro Microsystems, LLC

Inventor： Chung C. Kuo ,  Maxim Klebanov

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78 ,  H01L29/866 ,  H01L29/87

CPC classification number: H01L27/0259 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/0266 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7393 ,  H01L29/7412 ,  H01L29/7436 ,  H01L29/7821 ,  H01L29/861 ,  H01L29/866 ,  H01L29/87

Abstract: In one aspect, a silicon-controlled rectifier (SCR) includes a Zener diode embedded in the SCR. In another aspect, a laterally diffused metal oxide semiconductor (LDMOS) includes a Zener diode embedded in the LDMOS. In a further aspect, a lateral insulated-gate bipolar transistor (IGBT) includes a Zener diode embedded in the IGBT.

公开(公告)号：US12249646B2

公开(公告)日：2025-03-11

申请号：US17695029

申请日：2022-03-15

Applicant: Allegro MicroSystems, LLC

Inventor： Thomas S. Chung ,  Chung C. Kuo ,  Maxim Klebanov ,  Sundar Chetlur

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08

Abstract: In one aspect, a double-diffused metal oxide semiconductor (DMOS) includes a region of a semiconductor having a first region of a semiconductor having a first-type dopant, a first well having a second-type dopant, a dielectric within the first well, the dielectric having a bottom surface and a top surface opposite the bottom surface, a gate disposed on the top surface of the dielectric. The gate, the dielectric and the first well are configured to form a first reduced surface field (RESURF). The bottom surface of the dielectric has a first portion and a second portion, and the first portion of the bottom surface of the dielectric is closer to the top surface of the dielectric than the second portion of the bottom surface of the dielectric.

公开(公告)号：US20230299195A1

公开(公告)日：2023-09-21

申请号：US17695029

申请日：2022-03-15

Applicant: Allegro MicroSystems, LLC

Inventor： Thomas S. Chung ,  Chung C. Kuo ,  Maxim Klebanov ,  Sundar Chetlur

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/0852

Abstract: In one aspect, a double-diffused metal oxide semiconductor (DMOS) includes a region of a semiconductor having a first region of a semiconductor having a first-type dopant, a first well having a second-type dopant, a dielectric within the first well, the dielectric having a bottom surface and a top surface opposite the bottom surface, a gate disposed on the top surface of the dielectric. The gate, the dielectric and the first well are configured to form a first reduced surface field (RESURF). The bottom surface of the dielectric has a first portion and a second portion, and the first portion of the bottom surface of the dielectric is closer to the top surface of the dielectric than the second portion of the bottom surface of the dielectric.